3D Semiconductor Structure Via Formation
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Solution Overview
Problem
The existing methods for forming three-dimensional semiconductor structures through silicon via (TSV) technology often require multi-step etching processes, which can be complex and inefficient, especially when creating TSVs of different depths in the same etching process.
Innovation Solution
A method involving preparing a first device with a circuit and interlayer dielectric layer on a substrate, forming a through dielectric via, bonding with a second device, and performing an etching process on the back side of the substrate to simultaneously create via holes, allowing for the formation of via plugs that establish direct electrical connections without the need for an extra etch delay structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multi-step etching processes are used to form TSV structures, then the electrical connection between upper and lower electronic devices is achieved, but the process complexity increases
Solution Approach 1:
The patent combines multiple etching steps into a single etching process by using an etch delay structure that selectively delays etching in specific regions. This allows different via holes of different depths to be formed simultaneously in one etching step, reducing process complexity while maintaining reliable electrical connections between devices
2Productivity
If etch delay structure is embedded in the upper electronic device, then TSVs of different depths can be generated in the same etching process, but the device structure becomes more complex
Solution Approach 1:
The etch delay structure serves as an intermediary element that temporarily modifies the etching process. It is embedded in the upper electronic device to control etching depth selectively, enabling single-step formation of via holes with different depths. The etch delay structure acts as a mediator between the etching process and the final device structure, allowing process simplification while accepting temporary structural complexity
3Ease of operation
If a through dielectric via is formed and devices are bonded, then direct electrical connection from one surface is enabled, but additional etching steps are required
Solution Approach 1:
The patent performs preliminary actions by forming the through dielectric via and bonding the devices before completing the final etching steps. The etch delay structure is pre-formed in the upper device, and the through dielectric via is created before bonding. This sequence of preliminary actions enables the final single-step etching to complete the connection without requiring additional complex etching steps after bonding
Data Source
AI summary
A method of forming a three dimensional semiconductor structure includes: forming a through dielectric via extending on a first surface of a first interlayer dielectric layer of a first device; bonding the first device and a second device by the first surface and a second surface of the second device such that a through silicon contact pad on the second surface covers the through dielectric via; performing an etching process on a back side of a first substrate of the first device opposite to the first interlayer dielectric layer to simultaneously form a first via hole and a second via hole and exposing the second via hole through the through silicon contact pad; and forming a first via plug to fill the first via hole, and a second via plug to fill the second via hole and the through dielectric via.