Semiconductor Interconnection Layout Without Via Plugs
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Solution Overview
Problem
Current semiconductor devices face challenges in achieving high reliability and performance due to complexity and integration density limitations, particularly in reducing parasitic capacitance and connection resistance, which affect their electrical characteristics.
Innovation Solution
The semiconductor device incorporates a specific structure with active patterns, gate electrodes, source/drain patterns, interlayer insulating layers, and interconnection layers, including insulating structures and lines that directly connect to active and gate contacts without via plugs, reducing parasitic capacitance and improving electrical characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional fabrication processes are used with via plugs for interconnections, then manufacturing reliability is maintained through established processes, but parasitic capacitance and connection resistance increase, degrading electrical characteristics
Solution Approach 1:
The patent removes via plugs from the interconnection structure, extracting the harmful element that causes parasitic capacitance and resistance. The interconnection line directly contacts the active contact without requiring a via plug, thereby eliminating the source of electrical degradation while maintaining manufacturing reliability through the simplified structure.
Solution Approach 2:
The patent transitions from a vertical multi-layer via plug structure to a planar direct-contact structure. The interconnection line extends in the planar direction to directly contact the active contact, changing the dimensional approach from vertical stacking to lateral extension, thereby reducing parasitic effects.
2Reliability
If multiple via plugs and interconnection layers are used to achieve proper electrical connections, then connection reliability is ensured, but fabrication process complexity and potential for process failures increase
Solution Approach 1:
The patent segments the interconnection function into distinct components: the interconnection line and the active contact are separated in space but directly connected, eliminating the need for via plugs. This segmentation allows for simpler fabrication processes while maintaining connection reliability through direct contact geometry.
Solution Approach 2:
The active contact and interconnection line are designed with predetermined geometric configurations that ensure proper alignment and contact before final assembly. The protruding upper portion of the active contact and the extending interconnection line are pre-positioned to guarantee direct contact, eliminating the need for complex via plug alignment processes.
3Productivity
If via plugs are used to connect interconnection lines to active contacts, then manufacturing robustness is maintained through standard processes, but parasitic capacitance increases, reducing device performance
Solution Approach 1:
The patent converts the potential harm of direct exposure between interconnection elements into a benefit by designing the interconnection line to directly contact the active contact in a controlled manner. This direct contact eliminates parasitic capacitance that would otherwise be generated by via plug structures, turning the potential risk of direct exposure into a performance advantage.
Data Source
AI summary
A semiconductor device includes a first active pattern on a substrate; a first gate electrode crossing the first active pattern; source/drain patterns in an upper portion of the first active pattern and at opposite sides, respectively, of the first gate electrode; a first gate capping pattern on the first gate electrode; an interlayer insulating layer on the source/drain patterns; first and second active contacts penetrating the interlayer insulating layer and being respectively connected to the pair of source/drain patterns; and a first interconnection layer on the first and second active contacts. The first interconnection layer may include a first insulating structure covering a top surface of the second active contact; and a first interconnection line covering a top surface of the first active contact and extending on the first insulating structure, and covering a top surface of the first gate capping pattern between the first and second active contacts.