Semiconductor Via Geometry for Lower Resistance Heat Dissipation
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Solution Overview
Problem
High-power semiconductor devices face challenges in heat dissipation due to series resistance and dielectric residue in via structures, which hinder efficient heat dissipation and device performance.
Innovation Solution
The design involves a semiconductor substrate with specific geometric patterns in conductive vias that minimize dielectric residue, reducing series resistance and enhancing heat dissipation by optimizing the separation between geometric centers and using a process that fills via trenches with conductive materials without dielectric residue.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional via structures are used in high-power semiconductor devices, then manufacturing is simpler, but series resistance increases and heat dissipation deteriorates
Solution Approach 1:
The via structure is segmented into multiple geometric patterns (first geometric pattern, second geometric pattern, third geometric pattern) with distinct functions. The first pattern provides mechanical support, the second pattern optimizes electrical conductivity, and the third pattern enhances heat dissipation. This segmentation allows each component to be optimized independently for its specific function while maintaining overall manufacturability.
Solution Approach 2:
Different regions of the via structure are assigned different geometric patterns with locally optimized properties. The first geometric pattern has properties optimized for mechanical strength, the second for electrical conductivity, and the third for thermal conductivity. This local quality approach ensures that each part of the via structure contributes optimally to its specific function, resolving the contradiction between performance and manufacturing complexity.
2Reliability
If via trenches are completely filled with conductive materials, then series resistance decreases, but dielectric residue increases
Solution Approach 1:
The geometric patterns are designed in advance to create natural drainage pathways and void spaces that prevent dielectric residue accumulation before the filling process occurs. The specific geometric configurations (overlapping circles, hexagons, or triangles) are pre-planned to ensure complete evacuation of dielectric materials, eliminating the need for additional cleaning steps and preventing residue-related reliability issues.
Solution Approach 2:
The design converts the potential harm of complete via filling into a benefit by using the filling process itself to define the final geometric patterns. The conductive material fills the via trenches and conforms to the predetermined geometric patterns, which are specifically designed to exclude dielectric residue. This approach transforms the filling process from a potential source of residue into a method for creating precise, residue-free conductive structures.
3Area of moving object
If geometric patterns are placed closer together, then area is reduced, but series resistance increases due to dielectric residue
Solution Approach 1:
The geometric patterns extend into the vertical dimension with specific depth configurations and overlapping arrangements. By utilizing the third dimension (via trench depth), the design achieves horizontal compactness while maintaining vertical separation that prevents dielectric residue formation. The patterns are positioned at different depths or with varying thicknesses, allowing close horizontal spacing without compromising electrical performance.
Solution Approach 2:
The via structure employs composite geometric patterns combining different shapes (circles, hexagons, triangles) with complementary properties. These composite patterns are designed to interlock or overlap in ways that maximize space utilization while creating natural voids that prevent dielectric residue. The composite structure achieves both area reduction and series resistance minimization through synergistic geometric combinations.
Data Source
AI summary
The present disclosure provides a semiconductor substrate, including a first dielectric layer with a first surface and a second surface, a first conductive via extending between the first surface and the second surface, a first patterned conductive layer on the first surface, and a second patterned conductive layer on the second surface. The first conductive via includes a bottom pattern on the first surface and a second patterned conductive layer on the second surface. The bottom pattern has at least two geometric centers corresponding to at least two geometric patterns, respectively, and a distance between one geometric center and an intersection of the two geometrical patterns is a geometric radius. A distance between the at least two geometric centers is greater than 1.4 times the geometric radius. A method for manufacturing the semiconductor substrate described herein and a semiconductor package structure having the semiconductor substrate are also provided.