Semiconductor Package Via Group Layout for High-Density I/O Reliability
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Solution Overview
Problem
The increasing miniaturization of semiconductor chips and the need for higher I/O pad density in semiconductor dies complicates packaging, leading to issues such as limited I/O pad numbers, solder bridges, and reduced yield in conventional packaging technologies, especially in fan-in and fan-out packages.
Innovation Solution
A fan-out package design utilizing multi-via connections (via groups) that reduce stress and improve reliability by vertically misaligning via groups, allowing for increased I/O pad distribution and reducing stress-related distortions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If fan-in package is used with smaller die sizes, then throughput is improved and cost is reduced, but the number of I/O pads is limited due to pitch constraints and solder bridge risks
Solution Approach 1:
The patent transitions from a two-dimensional pad layout (fan-in) to a three-dimensional redistribution structure (fan-out) using multiple conductive layers and vias. This allows I/O pads to be distributed across multiple layers and a larger area, increasing the effective number of I/O pads without increasing the die footprint.
Solution Approach 2:
The patent implements nested conductive structures where multiple conductive layers are stacked vertically with vias connecting them. This nesting approach allows multiple I/O connections to be packed into a smaller horizontal footprint by utilizing the vertical dimension, effectively increasing the number of I/O pads.
2Quantity of substance
If I/O pad pitch is decreased to increase pad density, then more I/O pads can be packed, but solder bridges may occur
Solution Approach 1:
By redistributing I/O pads across multiple conductive layers in the vertical dimension, the horizontal pitch between pads on the same layer can be maintained at safe distances while still achieving high overall pad density through the stacked layer structure.
Solution Approach 2:
The patent segments the I/O pad connections into multiple separate conductive layers, with each layer containing a subset of the total I/O pads. This segmentation allows each layer to have adequate pad spacing to prevent solder bridges while the aggregate across all layers provides high total pad count.
3Quantity of substance
If fan-out package is used to redistribute I/O pads to greater area, then number of I/O pads can be increased, but packaging complexity increases
Solution Approach 1:
The complex fan-out packaging process is segmented into discrete, repeatable steps: forming first and second conductive layers, creating via holes, applying mandrels, and performing planarization. This segmentation makes the complex process more manageable and suitable for automated manufacturing.
Solution Approach 2:
The patent employs universal process steps and materials (e.g., spin-on-glass for planarization, standard photolithography for patterning) that can be applied across different package designs and sizes, reducing overall packaging complexity despite the increased I/O pad count.
4Reliability
If multiple conductive layers with via groups are used to reduce stress, then reliability is improved, but manufacturing process complexity increases
Solution Approach 1:
The stress management function is segmented into multiple conductive layers with via groups at different heights and positions. Each layer and via group independently contributes to stress distribution, and the modular structure allows for systematic manufacturing using standard multi-layer PCB techniques.
Solution Approach 2:
Via groups are strategically positioned at specific locations where stress concentration is expected, rather than uniformly distributing all vias throughout the structure. This local quality approach targets stress reduction where needed most while simplifying the overall manufacturing process.
Data Source
AI summary
A method includes placing a package component over a carrier, encapsulating the package component in an encapsulant, and forming a connection structure over and electrically coupling to the package component. The formation of the connection structure includes forming a first via group over and electrically coupling to the package component, forming a first conductive trace over and contacting the first via group, forming a second via group overlying and contacting the first conductive trace, wherein each of the first via group and the second via group comprises a plurality of vias, forming a second conductive trace over and contacting the second via group, forming a top via overlying and contacting the second conductive trace, and forming an Under-Bump-Metallurgy (UBM) over and contacting the top via.