Semiconductor Package Via Groups for High-Density Reliable I/O
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Solution Overview
Problem
The packaging of semiconductor dies becomes increasingly difficult due to the need for greater I/O pad density in smaller areas, leading to issues such as solder bridges and limited I/O pad numbers in conventional fan-in packages, and the inefficiency of fan-out packages in handling defective dies.
Innovation Solution
A fan-out package method is developed using multi-via connections (via groups) that reduce stress and improve reliability by vertically misaligning via groups, allowing for increased I/O pad density and efficient handling of defective dies through wafer-level packaging.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If fan-in packaging is used to maintain simpler packaging process, then packaging throughput is improved and cost is reduced, but the number of I/O pads is limited due to die area constraints
Solution Approach 1:
The patent transitions from planar I/O pad arrangement on the die surface to three-dimensional vertical stacking using multiple die layers connected through through-silicon vias (TSVs). This dimensional change allows I/O pads to be distributed across multiple layers, effectively increasing the total number of I/O pads without increasing the footprint area of individual dies.
Solution Approach 2:
The patent implements a stacked die architecture where multiple thin active dies are nested vertically, with each die containing I/O pads on its surface. The dies are interconnected through TSVs that pass through the substrate, creating a nested structure where I/O pads on different layers are vertically aligned or offset to maximize connectivity while minimizing lateral space requirements.
2Quantity of substance
If I/O pad pitch is decreased to increase I/O pad density, then the number of I/O pads is increased, but solder bridges occur
Solution Approach 1:
The patent resolves the solder bridge issue by moving the connection function from the lateral plane to the vertical dimension. TSVs provide direct vertical pathways through the substrate, allowing I/O pads to be connected without requiring closely spaced lateral traces. This vertical connectivity eliminates the need for dense lateral routing that would otherwise cause solder bridges.
Solution Approach 2:
The patent introduces TSVs as intermediary connection structures that mediate between I/O pads on different die layers. These vias act as vertical conductors that bypass the need for lateral trace routing, thereby eliminating the solder bridge problem associated with high-density lateral pad arrangements while enabling increased I/O pad density.
3Quantity of substance
If fan-out packaging is used to increase I/O pad density, then the number of I/O pads is increased, but defective dies cannot be efficiently handled
Solution Approach 1:
The patent implements wafer-level packaging where multiple dies are packaged together in a stacked configuration before individualization. This preliminary action allows for batch processing and testing, enabling efficient identification and removal of defective dies while maintaining the integrity of good dies. The stacked structure facilitates group handling and reduces the need for individual die manipulation.
Solution Approach 2:
The patent creates individually separable die stacks where each die can be independently tested and identified. The modular stacked structure allows defective dies to be detected and removed from the stack without affecting other dies, enabling efficient defect management while maintaining high I/O pad density through the vertical architecture.
4Adaptability or versatility
If more functions are integrated into smaller semiconductor dies, then device functionality is improved, but packaging difficulty increases
Solution Approach 1:
The patent resolves packaging complexity by transitioning to vertical stacking architecture. Multiple functional dies can be integrated in the vertical dimension, allowing increased device functionality without increasing lateral footprint. The standardized TSV connection method simplifies the packaging process despite the increased number of functions, as the vertical stacking approach provides a systematic method for interconnecting multiple functional layers.
Data Source
AI summary
A method includes placing a package component over a carrier, encapsulating the package component in an encapsulant, and forming a connection structure over and electrically coupling to the package component. The formation of the connection structure includes forming a first via group over and electrically coupling to the package component, forming a first conductive trace over and contacting the first via group, forming a second via group overlying and contacting the first conductive trace, wherein each of the first via group and the second via group comprises a plurality of vias, forming a second conductive trace over and contacting the second via group, forming a top via overlying and contacting the second conductive trace, and forming an Under-Bump-Metallurgy (UBM) over and contacting the top via.


