Semiconductor Via Hole Formation via Preliminary Etching
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Solution Overview
Problem
The existing semiconductor device manufacturing processes face challenges in simultaneously forming common and fourth through-holes without issues, such as short circuits or poor connections, due to different etching conditions required for each type of hole.
Innovation Solution
A method is introduced to form a semiconductor device with a stack structure of capacitive elements, where through-holes are formed in advance in specific regions, allowing for simultaneous etching of insulating layers and capacitance films while avoiding the electrodes, thus enabling the formation of multiple via holes under common conditions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If common through-holes and fourth through-holes are formed simultaneously in the same process, then the number of processes is reduced, but short circuits or poor connections occur due to different etching conditions required for each hole type
Solution Approach 1:
Through-holes are formed in advance in specific regions (second region B) before the simultaneous etching process. This preliminary action creates a structural distinction that allows the etching process to selectively form first via holes (passing through insulating layer and capacitance films) and second via holes (passing through insulating layer and capacitance film to contact intermediate electrode) under common etching conditions, while avoiding short circuits and ensuring proper connections
2Reliability
If different etching conditions are used for common through-holes and fourth through-holes, then proper connections are ensured, but the manufacturing process becomes complex
Solution Approach 1:
The patent applies local quality by creating a specific structural configuration where through-holes are pre-formed in the second region B. This local structural difference enables the etching process to naturally differentiate between first via holes and second via holes based on their positions relative to the pre-formed through-holes, allowing both hole types to be formed under common etching conditions without requiring different process parameters
Data Source
AI summary
A semiconductor device manufacturing method includes forming a first capacitance film formed on the lower electrode; forming an intermediate electrode in a first region on the first capacitance film, wherein the first capacitance is interposed between the intermediate electrode and the lower electrode; forming a second capacitance film on the intermediate electrode to be interposed between the first capacitance film and the second capacitance film; and forming an upper electrode, wherein at least a portion of the second capacitance film is interposed between the upper electrode and the intermediate electrode; the upper electrode extending to a second region outside the first region, and having at least the first capacitance film interposed between the upper electrode and the lower electrode in the second region.