Semiconductor Via Structure with Extended Intermediate Interconnection
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Solution Overview
Problem
In semiconductor devices with stacked interconnect layers, the existing via formation methods often result in misalignment between vias and interconnections due to the thinning of vias at connection locations, leading to insufficient contact area and increased contact resistance, especially when trying to maintain a large cross-section of intermediate interconnections.
Innovation Solution
The semiconductor device employs a via structure where the intermediate interconnection is left unetched and exposed on the top, bottom, and side surfaces of the through-hole, allowing for self-alignment and ensuring a larger contact area by embedding conductive materials directly into the through-hole, which connects the via with the intermediate interconnection on multiple surfaces.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the via connection portion is formed at the end portion of the intermediate interconnection to overlap the via region, then the via can be formed by etching the insulating film, but the via thins at the connection location causing misalignment between the via and interconnection
Solution Approach 1:
The intermediate interconnection is formed to extend beyond the via formation region in advance, before the via is formed. This preliminary extension ensures that when the via is subsequently formed by etching, the intermediate interconnection is already positioned to provide adequate overlap and alignment, eliminating the need for additional alignment margins while maintaining manufacturing simplicity.
2Manufacturing precision
If the intermediate interconnection is removed in the through-hole forming process to expose the end portion, then self-alignment is achieved, but the contact area between via and intermediate interconnection is reduced increasing contact resistance
Solution Approach 1:
Instead of removing the intermediate interconnection to achieve alignment, the invention inverts the approach by leaving the intermediate interconnection intact and extending it beyond the via region. This ensures both self-alignment through the extended portion and sufficient contact area through the overlapping region, simultaneously achieving precision and reliability.
3Manufacturing precision
If misalignment margin is added to the via and interconnection to reduce misalignment, then alignment is improved, but chip area increases
Solution Approach 1:
The intermediate interconnection is designed with non-uniform width, being wider at the via connection region and narrower at other portions. This local quality change allows the via connection region to provide sufficient overlap and alignment without increasing the overall chip area, as the wider section is localized only where needed for via connection.
Data Source
AI summary
A semiconductor device including: a semiconductor substrate; a plurality of interconnect layers disposed at different heights from the semiconductor substrate, each interconnect layer including an interconnection formed therein; and a via formed in a columnar shape extending in the stack direction of the interconnect layers, the via electrically connecting the interconnections of the different interconnect layers, the interconnections including an intermediate interconnection in contact with the via in the intermediate portion thereof, and the intermediate interconnection including a first type intermediate interconnection passing through the via in a direction perpendicular to the stack direction and in contact with the via on the top surface, bottom surface, and both side surfaces thereof.