Semiconductor Via Etching With Isolation Etch Stops
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Solution Overview
Problem
Existing semiconductor manufacturing methods face challenges in controlling the etching rate difference of via openings with varying widths, leading to potential interference with transistors and limiting the density of transistor arrangement.
Innovation Solution
A method is employed to control the etching rate difference by using an isolation structure as an etch stop layer for wider via openings, with controlled etching processes to form vias of varying widths, including a narrow bottom portion for signal vias to minimize interference with transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If conventional etching processes are used to form via openings of varying widths, then wider via openings can be formed to accommodate power vias, but the etching time difference between vias of different widths increases, leading to potential interference with transistors
Solution Approach 1:
An isolation structure is formed at the bottom of the substrate before etching the via openings. This preliminary structure serves as an etch stop layer that terminates the etching process at a predetermined depth, preventing over-etching and reducing the etching time difference between vias of different widths
Solution Approach 2:
The isolation structure acts as an intermediary element between the etching process and the transistors. It provides a physical barrier that stops the etching process, thereby protecting the transistors from damage while allowing via openings of varying widths to be formed
2Manufacturing precision
If wider via openings are formed to reduce etching time difference, then power vias can be accommodated, but transistor interference increases and transistor density decreases
Solution Approach 1:
The isolation structure is formed in advance at the target depth location, serving as a pre-positioned etch stop that precisely controls etching depth and prevents damage to underlying transistors
Solution Approach 2:
The isolation structure functions as a protective intermediary layer between the etching process and the transistors, absorbing the harmful effects of the etchant and preventing direct contact with the transistor structures
3Object-affected harmful factors
If multiple etching processes are used to control via depths, then transistor interference is reduced, but the manufacturing process complexity increases
Solution Approach 1:
The isolation structure is formed once before all etching operations, providing a permanent etch stop that eliminates the need for multiple separate etching processes to control via depths
Solution Approach 2:
The isolation structure serves multiple functions simultaneously: it acts as an etch stop for all via openings regardless of width, protects all transistors from etching damage, and enables the formation of both narrow signal vias and wide power vias in a single etching process
Data Source
AI summary
A method of manufacturing a semiconductor device includes bonding a first wafer with a second wafer. The second wafer includes a substrate, an isolation structure in the substrate, a transistor on the substrate, and a interconnect structure over the second transistor. A first etching process is performed to form a first via opening and a second via opening in the substrate. The second via opening extends to the isolation structure, and the second via opening is deeper than the first via opening. A second etching process is performed such that the first via opening exposes the substrate. A third etching process is performed such that the first via opening and the second via opening exposes the interconnect structure, and the second via opening penetrates the isolation structure. A first via is formed in the first via opening and a second via is formed in the second via opening.