Semiconductor Device Via Layout for Crack Prevention
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Solution Overview
Problem
Conventional semiconductor devices face issues with peeling between wiring and interlayer insulating films due to stress, leading to reliability concerns and conduction failures, particularly during the formation and operation of thicker wiring layers.
Innovation Solution
The semiconductor device incorporates a structure with thicker second wiring and strategically arranged dummy vias, where the distance between dummy vias and corner portions is optimized to redirect stress-induced cracks away from primary vias, enhancing the structural integrity and preventing open defects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If the wiring film thickness is increased to flow large current, then the current carrying capacity is improved, but the stress concentration and peeling between wiring and interlayer insulating film worsen
Solution Approach 1:
The patent divides the via structure into two types: first vias for electrical connection and second vias (dummy vias) for stress management. This segmentation allows the via system to simultaneously fulfill electrical connection functions and stress distribution functions, preventing peeling between the thick wiring and interlayer insulating film while maintaining high current carrying capacity.
Solution Approach 2:
The second vias act as intermediary elements between the thick wiring and the interlayer insulating film. These dummy vias do not primarily serve electrical connection purposes but rather mediate the stress distribution, preventing direct stress concentration at the wiring-insulating film interface and thereby preventing peeling.
2Reliability
If dummy vias are placed close to wiring corner portions to redirect cracks, then the reliability is improved, but the manufacturing precision requirement increases
Solution Approach 1:
The second vias are placed in advance at predetermined positions near the corner portions of the wiring during the design and manufacturing process. This preliminary placement ensures that if cracks occur during subsequent polishing or operation, they will be redirected toward the dummy vias rather than propagating through the first vias or causing peeling, thus improving reliability while maintaining manageable manufacturing precision requirements.
Data Source
AI summary
The semiconductor device SD1a includes a first wiring M2 and a second wiring M3. The semiconductor device includes a first conductor pattern DM, a first via V2 in contact with the first wiring M2 and the second wiring M3, and a second via DV1,DV2,DV3,DV4 in contact with the first conductor pattern DM and the second wiring M3. In plan view, the distance between the second via DV1 closest to the corner portion CI of the second wire M3 and the corner portion CI is shorter than the distance between the first via V2 and the corner portion CI, and the distance between the second vias adjacent to each other is shorter than the distance between the second via DV3 closest to the first via V2 and the first via V2.