Semiconductor Via Layout for Temperature-Cycle Connection Reliability
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Solution Overview
Problem
The reliability of electrical connections between the wiring layer and the electrodes of semiconductor elements in semiconductor devices is compromised, particularly in the peripheral regions due to stress and deformation during temperature cycling tests.
Innovation Solution
The semiconductor device incorporates via wirings of varying planar sizes, with larger wirings in the peripheral regions and smaller wirings in the central regions, ensuring stable electrical connections by minimizing stress concentration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If uniform via wirings are used throughout the semiconductor device, then manufacturing is simplified, but stress concentration occurs in peripheral regions during temperature cycling leading to reduced connection reliability
Solution Approach 1:
The patent applies local quality by configuring via wirings with different planar sizes at different locations: larger planar sizes in peripheral regions to handle stress concentration, and smaller planar sizes in central regions. This localized differentiation optimizes stress distribution and connection reliability without requiring complete redesign of the entire via wiring system.
Solution Approach 2:
The patent changes the planar size parameter of via wirings based on their location within the semiconductor device. By adjusting this geometric parameter according to stress distribution patterns (larger at periphery, smaller at center), the design adapts to local mechanical conditions while maintaining manufacturing feasibility.
2Reliability
If larger via wirings are used in peripheral regions to reduce stress concentration, then connection reliability improves, but manufacturing precision requirements increase
Solution Approach 1:
The patent segments the via wiring population into different size categories based on location: larger via wirings for peripheral regions experiencing high stress, and smaller via wirings for central regions. This segmentation allows each group to be optimized for its specific mechanical environment while using standard manufacturing processes.
Solution Approach 2:
By assigning different planar sizes to via wirings in different locations, the patent addresses the specific stress conditions of peripheral regions without imposing uniform high-precision requirements across the entire device. The larger peripheral via wirings provide stress relief while the varied configuration remains compatible with existing manufacturing capabilities.
Data Source
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AI summary
A semiconductor device (10) includes a lower substrate (20), a semiconductor element (30) mounted on an upper surface of the lower substrate (20), and an upper substrate (40) arranged on an upper surface of the semiconductor element (30). The semiconductor element (30) includes an electrode (32) arranged on the upper surface of the semiconductor element (30). The semiconductor device (10) includes via wirings (80) and a wiring layer (60). The via wirings (80) extend through the upper substrate (40) in a thickness-wise direction and are connected to the electrode (32). The wiring layer (60) is arranged on an upper surface of the upper substrate (40) and is electrically connected to the electrode (32) by the via wirings (80). The via wirings (80) include two or more types of via wirings (80:81,82,83) that differ from one another in planar size. The via wirings (80) are arranged so that the planar size decreases from a peripheral portion of the semiconductor element (30) toward a central portion of the semiconductor element (30) in plan view.