Semiconductor Device Via Liner Insulation Shorting Prevention
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Solution Overview
Problem
The existing methods for forming through-silicon vias in semiconductor devices often result in shorting between wiring and semiconductor elements due to excessive polishing of liner insulating films, which compromises the reliability and performance of the devices.
Innovation Solution
A semiconductor device design that uses a thick liner insulating film made of SiOC as an interlayer insulating film for the first wiring layer, which reduces capacitance between the semiconductor substrate and the through-silicon via, and eliminates the need for a pad to cover the upper surface of the via, thereby preventing shorting and improving manufacturing reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the liner insulating film is removed by polishing to complete the through-silicon via, then the via is completed, but the interlayer insulating film becomes thin, resulting in shorting
Solution Approach 1:
The liner insulating film is preliminarily formed to extend beyond the via opening during the via formation process. This preliminary extension ensures that when polishing is performed to complete the via, the insulating film remains sufficiently thick to prevent shorting, while still allowing the via to be properly formed
Data Source
AI summary
A semiconductor device with a through via penetrating a semiconductor substrate, in which shorting between a wiring and a semiconductor element is prevented to improve the reliability of the semiconductor device. A liner insulating film as a low-k film, which has a function to insulate the semiconductor substrate and a through-silicon via from each other and is thick enough to reduce capacitance between the semiconductor substrate and the through-silicon via, is used as an interlayer insulating film for a first wiring layer over a contact layer. This prevents a decrease in the thickness of an interlayer insulating film in the contact layer.


