Semiconductor Via Liner Resistance Reduction
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Solution Overview
Problem
As semiconductor technology advances, metal via resistance increases due to shrinking component features, and Time Dependent Dielectric Breakdown (TDDB) occurs due to misalignment and diffusion issues in metal interconnects, leading to reliability failures in semiconductor devices.
Innovation Solution
A semiconductor interconnect structure with a dielectric and metal capping layer is introduced, where the high resistivity liner material at the bottom of metal vias is selectively removed and replaced with a low resistivity liner material, and a diffusion barrier is formed to prevent ion diffusion and electrical shorts, reducing via resistance and enhancing reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high resistivity liner material is used at the bottom of metal vias, then diffusion barrier properties are improved, but via resistance increases
Solution Approach 1:
The patent applies different liner materials with different resistivity characteristics to different locations within the via structure. High resistivity liner material is used at the via sidewalls for diffusion barrier properties, while low resistivity liner material is used at the via bottom to reduce contact resistance. This local differentiation resolves the contradiction by optimizing each region's material properties according to its specific functional requirements.
2Productivity
If metal interconnect features are shrunk to improve device density, then productivity is improved, but via resistance increases
Solution Approach 1:
The patent changes the resistivity parameter of the liner material at the via bottom by selecting low resistivity materials specifically for this location. This parameter change compensates for the increased via resistance that occurs when via dimensions are reduced during technology scaling, thereby maintaining acceptable electrical performance while achieving higher device density.
3Ease of manufacture
If misalignment occurs in metal interconnects, then manufacturing complexity is reduced, but TDDB failures increase
Solution Approach 1:
The patent employs a liner material structure that provides a buffer or cushioning effect against misalignment. The liner material at the via bottom creates a larger effective contact area and provides tolerance for alignment variations, preventing direct metal-to-dielectric contact that would lead to TDDB failures. This beforehand cushioning allows greater alignment tolerance while maintaining reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution reduces metal via resistance and minimizes TDDB defects, resulting in superior performance and reliability for semiconductor applications by ensuring reproducible and manufacturable designs.
Implementation Method 1
replaced with a low resistivity liner material, reducing via resistance
Implementation Method 2
a diffusion barrier is formed to prevent ion diffusion and electrical shorts
Data Source
AI summary
A semiconductor interconnect structure having a first electrically conductive structure having a plurality of bottom portions; a dielectric capping layer, at least a portion of the dielectric capping layer being in contact with a first bottom portion of the plurality of bottom portions; and a second electrically conductive structure in electrical contact with a second bottom portion of the plurality of bottom portions. A method of forming the interconnect structure is also provided.