Semiconductor Vias via Lithography Mask Voids
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Solution Overview
Problem
The semiconductor industry faces challenges in accurately patterning conductive lines and vias due to diffraction effects in lithography, leading to incomplete via coverage and reduced current drivability in semiconductor devices, especially when dealing with wide conductive lines.
Innovation Solution
Incorporating voids in the conductive line patterns proximate via contact regions to improve alignment and pattern transfer, ensuring that vias fully land on the conductive lines, which is achieved by modifying the lithography mask designs to include voids in the pattern for the second material layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional lithography masks are used without voids, then the manufacturing process is simple, but via alignment to conductive lines is inaccurate and via coverage is incomplete
Solution Approach 1:
The conductive line pattern in the lithography mask is segmented by introducing voids (disconnected regions) within the pattern. This segmentation allows the pattern to be transferred more accurately to the conductive line layer, enabling better via alignment. The voids divide the continuous conductive line pattern into sections, which helps compensate for lithography diffraction effects and improves the precision of via placement relative to the actual conductive lines.
2Productivity
If feature sizes are reduced to improve device performance, then device performance improves, but pattern transfer accuracy deteriorates due to diffraction effects
Solution Approach 1:
The lithography mask pattern is pre-modified by adding voids before the lithography process. This preliminary action compensates for anticipated diffraction effects that will occur during pattern transfer. By预先 designing the mask with voids in specific locations, the actual transferred pattern achieves better alignment accuracy despite the reduced feature sizes, thus maintaining manufacturing precision while enabling higher device performance.
3Reliability
If voids are added to conductive line patterns, then via coverage and alignment improve, but the lithography mask design becomes more complex
Solution Approach 1:
Voids are not added uniformly throughout the entire conductive line pattern, but only in specific local regions where via contact is required. This local modification approach improves via coverage and alignment precision at critical locations without unnecessarily complicating the entire lithography mask design. The voids are strategically placed only where they provide benefit, maintaining simplicity in regions where they are not needed.
Data Source
AI summary
Semiconductor devices, methods of manufacturing thereof, lithography masks, and methods of designing lithography masks are disclosed. In one embodiment, a semiconductor device includes a plurality of first features disposed in a first material layer. At least one second feature is disposed in a second material layer, the at least one second feature being disposed over and coupled to the plurality of first features. The at least one second feature includes at least one void disposed between at least two of the plurality of first features.