Semiconductor Package Via Openings That Block Moisture Gaps

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Solution Overview

Problem

Existing semiconductor device packaging methods face challenges in achieving smaller package sizes while ensuring reliability and preventing water vapor penetration, particularly due to recesses and gaps in molding material layers.

Innovation Solution

The method involves forming openings in the insulating material layer with a width smaller than the through-vias, which prevents recesses and gaps, enhancing package reliability and preventing water vapor ingress.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If openings in insulating material layer have the same width as through-vias, then manufacturing is simpler, but recesses and gaps form causing water vapor penetration and reduced reliability

Engineering Contradiction:

Improvepackage reliabilityVSAvoidopening width design

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies local quality by making the opening width in the insulating material layer locally smaller than the through-via width. This creates a tapered structure where the opening width varies through the thickness of the insulating material, preventing recesses and gaps at the interface between molding material and through-vias, thereby eliminating water vapor penetration paths while maintaining manufacturing feasibility.

Inventive Principle:

Principle #3Local quality

2Area of stationary object

If package size is reduced to meet smaller electronic components, then area utilization improves, but structural integrity and reliability become more difficult to maintain

Engineering Contradiction:

Improvepackage areaVSAvoidstructural integrity

Core Design Contradiction:

Area of stationary objectVSReliability

Solution Approach 1:

The patent applies parameter changes by modifying the geometric parameters of the opening in the insulating material layer. Specifically, the opening width is made smaller than the through-via width, creating a tapered configuration that prevents gap formation. This parameter adjustment maintains structural integrity and prevents water vapor penetration even in reduced-size packages, thereby preserving reliability while achieving compact dimensions.

Inventive Principle:

Principle #35Parameter changes

3Reliability

If molding material is applied to fill through-vias, then via coverage is improved, but recesses and gaps still form at interfaces allowing water vapor ingress

Engineering Contradiction:

Improveprotection against water vaporVSAvoidmolding material application

Core Design Contradiction:

ReliabilityVSEase of manufacture

Solution Approach 1:

The patent applies preliminary action by pre-configuring the opening width in the insulating material layer to be smaller than the through-via width before applying the molding material. This preliminary dimensional adjustment ensures that when molding material is applied, it cannot form recesses or gaps at the interface, thereby preventing water vapor penetration paths from forming in the first place.

Inventive Principle:

Principle #10Preliminary action

Data Source

PatentUS20250316563A1Methods of packaging semiconductor devices and packaged semiconductor devices

Publication Date: 2025.10.09 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

Methods of packaging semiconductor devices and packaged semiconductor devices are disclosed. In some embodiments, a method of packaging a semiconductor device includes coupling through-vias to an insulating material, each of the through-vias having a first width. Dies are also coupled to the insulating material. A portion of the insulating material is removed proximate each of the through-vias. The portion of the insulating material proximate each of the through-vias removed has a second width, the second width being less than the first width.