Semiconductor Via Multi-Surface Contact Reliability

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Solution Overview

Problem

Current semiconductor apparatuses face challenges in achieving high connection reliability and miniaturization due to limitations in contact area and resistance at via interfaces, particularly in chip size package (CSP) types with through-hole wiring.

Innovation Solution

The semiconductor apparatus features a semiconductor device with a via having an opening at a second main surface, where a first wiring on the first main surface forms part of the via's bottom surface, covered by a first insulating layer, and a redistribution wiring extending through the via to the second main surface, with a through hole in the wiring allowing contact with multiple surfaces of the wiring, enhancing connection reliability.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Volume of moving object

If a through-hole wiring structure is used in CSP type semiconductor apparatus, then miniaturization and reduced thickness are achieved, but connection reliability and contact resistance at via interfaces deteriorate

Engineering Contradiction:
Improvesemiconductor apparatus sizeVSAvoidconnection reliability
Core Design Contradiction:
Volume of moving objectVSReliability

Solution Approach 1:

The invention transforms the contact interface from a single-plane contact to a multi-surface contact by creating a through hole in the wiring that extends vertically through the insulating layer. The redistribution wiring contacts the first wiring at multiple surfaces including the bottom surface and side surfaces within the through hole, effectively adding a vertical dimension to the contact interface and increasing the contact area without increasing the horizontal footprint.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The invention segments the contact interface into multiple contact regions distributed along the through hole walls. Instead of a single continuous contact area, the redistribution wiring makes discrete contacts at multiple locations along the vertical walls of the through hole, creating segmented contact points that collectively provide enhanced connection reliability and reduced contact resistance.

Inventive Principle:
Principle #1Segmentation

2Reliability

If contact area at via interface is increased, then connection reliability improves, but device complexity and manufacturing difficulty increase

Engineering Contradiction:
Improveconnection reliabilityVSAvoidvia structure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The through hole structure serves multiple functions simultaneously: it acts as an insulating barrier between the first wiring and the redistribution wiring, provides vertical spacing for signal integrity, and creates multiple contact surfaces for reliable electrical connection. This multi-functional design achieves enhanced connection reliability without proportionally increasing device complexity, as the same structural element fulfills multiple roles.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The insulating layer forming the through hole walls acts as an intermediary between the first wiring and the redistribution wiring. It provides electrical isolation while allowing controlled contact points to be established, mediating the interaction between the two conductive elements and enabling reliable connection through defined contact regions rather than direct extensive contact.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS10665538B2Semiconductor device
Publication Date: 2020.05.26 OLYMPUS CORPORATION(JP)
  • US10665538B2 patent drawing
  • US10665538B2 patent drawing
  • US10665538B2 patent drawing

AI summary

A semiconductor apparatus includes a semiconductor device having a semiconductor circuit formed on a first main surface, and including a via having an opening at a second main surface, a first wiring disposed on the first main surface of the semiconductor device, partially exposed at a bottom surface of the via, and connected to the semiconductor circuit, a first insulating layer covering the first wiring, and a redistribution wiring extending from a contact portion in contact with the first wiring at the bottom surface of the via, through an inside of the via and onto the second main surface, where a first through hole is formed in the first wiring, and the contact portion is in contact with a plurality of surfaces of the first wiring.