Semiconductor Via Pad Structure for Oxidation-Stable Interconnects

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Solution Overview

Problem

Conventional semiconductor structures face challenges in maintaining conductivity and stability due to oxidation of conductive pads and high aspect ratios of via structures, leading to reduced yield rates during manufacturing.

Innovation Solution

The semiconductor structure employs a first conductive pad with a second conductive pad of lower chemical reactivity, formed of different materials, to protect against oxidation and reduce the aspect ratio of via structures by using a dielectric layer and forming the second conductive pad in an opening, ensuring increased conductivity and stability.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a conventional single-layer conductive pad structure is used, then the manufacturing process is simple, but the conductive pad is prone to oxidation and conductivity deteriorates

Engineering Contradiction:
Improveconductivity stabilityVSAvoidconductive pad structure
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies composite materials by forming a multi-layer conductive pad structure where a first conductive pad (e.g., copper with high conductivity) is combined with a second conductive pad (e.g., tungsten or gold with low chemical reactivity). This composite structure maintains high conductivity while the second layer protects against oxidation, resolving the contradiction between reliability and simplicity.

Inventive Principle:
Principle #40Composite materials

Solution Approach 2:

The second conductive pad acts as an intermediary protective layer between the first conductive pad and the external environment. This mediator layer prevents direct exposure of the highly reactive first conductive pad to oxidizing conditions, thereby maintaining conductivity stability without requiring complex protective measures.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Manufacturing precision

If a via structure with high aspect ratio is used, then the vertical connection is achieved, but the yield rate decreases due to manufacturing difficulties

Engineering Contradiction:
Improvevia structure formationVSAvoidyield rate
Core Design Contradiction:
Manufacturing precisionVSProductivity

Solution Approach 1:

The patent changes the geometric parameters of the via structure by reducing the aspect ratio through optimized via diameter and depth dimensions. This parameter adjustment makes the via structure more manufacturable with standard processes, thereby increasing yield rate while still achieving the required vertical electrical connection functionality.

Inventive Principle:
Principle #35Parameter changes

3Reliability

If the second conductive pad is formed with greater thickness, then oxidation protection is enhanced, but the aspect ratio of via structures increases

Engineering Contradiction:
Improveoxidation protectionVSAvoidaspect ratio of via structure
Core Design Contradiction:
ReliabilityVSShape

Solution Approach 1:

The patent optimizes the thickness parameter of the second conductive pad to achieve the minimum required protection against oxidation while keeping the via aspect ratio within manufacturable limits. This balanced parameter selection resolves the contradiction between adequate protection and acceptable via geometry.

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The second conductive pad is strategically positioned and dimensioned to provide localized protection exactly where needed at the via interface, rather than uniformly throughout. This localized quality approach provides sufficient oxidation protection without unnecessarily increasing the via aspect ratio.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS12183715B2Method for manufacturing semiconductor structure
Publication Date: 2024.12.31 NAN YA TECH
  • US12183715B2 patent drawing
  • US12183715B2 patent drawing
  • US12183715B2 patent drawing

AI summary

The present disclosure provides a method for manufacturing a semiconductor structure employing a via structure. The method includes forming a first conductive pad on a first semiconductor device; forming a second conductive pad on the first conductive pad; connecting a second semiconductor device to the first semiconductor device; and forming a via structure in the second semiconductor device, The via structure contacts the second conductive pad, and the first conductive pad and the second conductive pad are formed of different metal materials.