3D Semiconductor Package Via Planarization for Die Alignment
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Solution Overview
Problem
Manufacturing variations in three-dimensional semiconductor packages can result in through interposer vias (TIVs) being shorter than others, leading to electrical connection failures and misalignment during device die placement due to recessed terminals and offset dome vertices.
Innovation Solution
A manufacturing method involving the formation of through via structures and dipole structures with insulating cores and conductive layers, where the through via structures are used to transmit signals and the dipole structures function as antennas, ensuring flat front surfaces and reduced height variation to prevent recession and misalignment, and the use of encapsulants to laterally encapsulate these structures and semiconductor dies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If through interposer vias are formed using conventional manufacturing processes, then signal transmission between device dies is enabled, but manufacturing variations cause height differences leading to recessed terminals and electrical connection failures
Solution Approach 1:
The patent applies preliminary action by forming a planarization layer over the through interposer vias before attaching device dies. This pre-flattening step ensures that subsequent die attachments occur on a uniform surface, preventing recessed terminal issues and electrical connection failures caused by via height variations.
Solution Approach 2:
The patent changes the physical state and properties of the interposer surface by introducing a planarization layer with specific material characteristics. This layer modifies the surface topology parameter from uneven to flat, thereby compensating for via height variations and ensuring reliable electrical connections.
2Measurement precision
If through interposer vias are used as alignment references during device die placement, then alignment positioning is enabled, but dome vertex offset causes misalignment of device dies
Solution Approach 1:
The patent applies preliminary action by forming a planarization layer that flattens the interposer surface before device die attachment. This pre-flattening eliminates dome vertex offsets, ensuring that alignment references are accurately positioned and device dies are correctly aligned during placement.
Solution Approach 2:
The planarization layer acts as an intermediary between the through interposer vias and the device dies. It mediates the alignment process by providing a flat reference surface that eliminates shape irregularities, thereby enabling precise alignment without being affected by dome vertex positions.
3Ease of manufacture
If conventional via structures are formed without planarization, then manufacturing process simplicity is maintained, but height variation causes both electrical connection failures and alignment misalignment
Solution Approach 1:
The patent introduces a planarization layer as a preliminary step in the manufacturing process. While this adds one more process step, it significantly improves package assembly reliability by preventing both electrical connection failures and alignment misalignment, thereby reducing rework and yield losses.
Solution Approach 2:
The planarization layer serves as a cushioning layer that compensates for via height variations before device die attachment. This beforehand cushioning prevents potential connection and alignment issues, thereby enhancing overall package reliability without significantly complicating the manufacturing process.
Data Source
AI summary
A semiconductor package and a manufacturing method are provided. The manufacturing method includes: forming a through via structure and a dipole structure over a carrier, wherein the through via structure and the dipole structure respectively include an insulating core and a conductive layer covering the insulating core; attaching a semiconductor die onto the carrier, wherein the through via structure and the dipole structure are located aside the semiconductor die; laterally encapsulating the though via structure, the dipole structure and the semiconductor die with an encapsulant; and removing the carrier.