Semiconductor Packaging Via Plating Without Planarization
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Solution Overview
Problem
The miniaturization of semiconductor chips poses challenges in adhering, handling, and testing solder balls, as well as accommodating diverse mounting boards, due to their small size, leading to difficulties in defect reduction and efficient fabrication processes.
Innovation Solution
A method involving a carrier substrate with a conductive layer, an insulating layer, and a seed layer is used to form via holes and redistribution layers, allowing for the fabrication of semiconductor devices with reduced defects by avoiding voids and filling failures during plating processes, and eliminating the need for planarization steps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the size of semiconductor chip becomes smaller with high integration, then integration capacity is improved, but handling and testing of solder balls becomes difficult
Solution Approach 1:
The patent transitions from traditional chip-scale solder ball attachment to a wafer-level process where multiple chips are processed simultaneously on a carrier substrate. This dimensional scaling allows solder balls to be handled and tested at the wafer level rather than individual chip level, resolving the handling difficulty while maintaining high integration capacity through multi-chip arrays.
Solution Approach 2:
The carrier substrate with conductive layer and insulating layer structure enables self-aligned via hole formation and automatic electrical connection establishment. The pre-configured conductive and insulating layers on the carrier substrate guide the self-service alignment and connection process, eliminating complex manual handling steps for small solder balls.
2Reliability
If via holes are formed to penetrate insulating layer, then electrical connection is achieved, but voids and filling failures occur during plating process
Solution Approach 1:
The patent applies preliminary plating to form a copper seed layer in the via holes before the main plating process. This preliminary action ensures that the via hole walls are pre-coated with conductive material, preventing void formation and filling failures during subsequent plating steps, while establishing reliable electrical connections.
Solution Approach 2:
The patent replaces mechanical via hole filling methods with electrochemical plating processes. By using electroless and electroplating techniques, copper is deposited chemically and electrically within the via holes, ensuring uniform filling without voids or filling failures that plague mechanical filling methods.
3Reliability
If carrier substrate with conductive layer and insulating layer is used, then defect reduction is achieved, but process complexity increases
Solution Approach 1:
The carrier substrate is designed as a multi-functional platform that simultaneously provides mechanical support, electrical connection pathways through conductive layers, and insulation through insulating layers. This universal structure performs multiple functions in one component, reducing overall process complexity despite the added defect reduction capabilities.
Solution Approach 2:
The patent segments the fabrication process into distinct modules: carrier substrate preparation with conductive and insulating layers, semiconductor chip mounting, via hole formation, and plating. This segmentation allows each module to be optimized independently, managing process complexity through systematic breakdown while maintaining defect reduction benefits.
4Productivity
If planarization steps are eliminated, then manufacturing efficiency is improved, but surface flatness may be compromised
Solution Approach 1:
The patent performs preliminary planarization by forming a flattened surface on the carrier substrate before mounting semiconductor chips. This preliminary action ensures that subsequent redistribution layers can be formed without requiring additional planarization steps, maintaining surface flatness while improving manufacturing efficiency by eliminating later planarization operations.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method reduces defects and improves the handling and testing of semiconductor chips by enabling efficient redistribution layer formation without planarization, thus enhancing the manufacturing process and chip integration.
Implementation Method 1
performing a plating process in which the conductive layer of the carrier substrate is used as a seed to form a via filling the via hole
Implementation Method 2
forming a seed layer to cover a bottom surface and an inner lateral surface of the via hole
Data Source
AI summary
Disclosed are semiconductor devices and methods of fabricating the same. The method comprises providing a carrier substrate that includes a conductive layer, placing a semiconductor die on the carrier substrate, forming an insulating layer to cover the semiconductor die on the carrier substrate, forming a via hole to penetrate the insulating layer at a side of the semiconductor die and to expose the conductive layer of the carrier substrate, performing a plating process in which the conductive layer of the carrier substrate is used as a seed to form a via filling the via hole, forming a first redistribution layer on a first surface of the semiconductor die and the insulating layer, removing the carrier substrate, and forming a second redistribution layer on a second surface of the semiconductor die and the insulating layer, the first surface and the second surface being located opposite each other.