Semiconductor Via Plug Tilt Angle for Low Resistance
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Solution Overview
Problem
In semiconductor devices, particularly isolators with magnetic coils, achieving low resistance connections between wiring layers through thick insulating layers is challenging due to void formation and increased resistance, which hinders efficient signal transmission.
Innovation Solution
A semiconductor device structure incorporating a silicon nitride layer, a thicker silicon oxide layer, and a thicker silicon oxynitride layer, with a via plug having specific tilt angles to enhance metal embeddability and reduce connection resistance, utilizing copper conductive layers and a protective insulating layer to strengthen magnetic coupling and signal transmission.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a thick insulating layer is used to secure withstand voltage between coils, then electrical insulation is improved, but connection resistance increases and signal transmission delay worsens
Solution Approach 1:
The patent changes the physical and chemical parameters of the insulating layer by introducing a gradient structure with varying silicon oxide content. The insulating layer transitions from high silicon oxide content (better insulation) near the first coil to low silicon oxide content (lower resistance) near the second coil, optimizing both withstand voltage and connection resistance simultaneously
Solution Approach 2:
The patent applies different material compositions to different regions of the insulating layer. The region closer to the first coil has higher silicon oxide content for superior insulation, while the region closer to the second coil has lower silicon oxide content to reduce resistance, creating a spatially varying local quality that addresses both requirements
2Reliability
If metal is embedded in connection holes to connect wiring layers, then electrical conduction is achieved, but void formation increases and connection reliability decreases
Solution Approach 1:
The patent modifies the chemical composition parameter of the insulating layer by creating a gradient in silicon oxide content. This parameter change improves metal embeddability by reducing void formation, as the lower silicon oxide content regions facilitate better metal infiltration and adhesion in the connection holes
Solution Approach 2:
The patent uses a composite insulating layer structure combining silicon oxide and silicon nitride in varying proportions. This composite material approach leverages the advantages of both materials: silicon oxide for insulation and silicon nitride for mechanical strength and void prevention, creating a synergistic effect that improves both conduction and reliability
Data Source
AI summary
A semiconductor device of the embodiment includes first and second conductive layer; a silicon nitride layer between the first conductive layer and the second conductive layer; a silicon oxide layer between the silicon nitride layer and the second conductive layer; a silicon oxynitride layer between the silicon oxide layer and the second conductive layer; and a third conductive layer between the first conductive layer and the second conductive layer, the third conductive layer electrically connected to the first and second conductive layer, a first tilt angle of a plane where the third conductive layer is in contact with the silicon oxynitride layer with respect to an interface between the silicon nitride layer and the silicon oxide layer is smaller than a second tilt angle of a plane where the third conductive layer is in contact with the silicon oxide layer with respect to the interface.