Semiconductor Via Openings With Polyimide Stress Relief
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Solution Overview
Problem
As semiconductor technology advances, the decreasing geometrical size of interconnect structures in ICs leads to increased parasitic capacitance and signal delay, cross-talk, and manufacturing defects such as voids and kinks, which weaken the mechanical strength and electrical properties of semiconductor devices.
Innovation Solution
A method is introduced to form semiconductor devices with improved stress relief by forming metal redistribution layers (RDLs) within via holes, using specific interior angles for passivation layers and polyimide openings to reduce stress and prevent defects, including descum and pull-back processes to enhance the structural integrity of the semiconductor device.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the geometrical size of interconnect structures is decreased to increase integration density, then the integration density is improved, but parasitic capacitance and signal delay increase
Solution Approach 1:
The patent applies different dielectric materials with different dielectric constants to different regions. Low-k dielectric material is used in specific areas where parasitic capacitance needs to be reduced, while other regions may use different materials optimized for their specific functions. This local differentiation allows reduction of harmful parasitic effects without compromising overall integration density.
Solution Approach 2:
The patent employs composite dielectric structures combining multiple materials including low-k dielectric material, organic dielectric material, and inorganic dielectric material. These composite structures are designed to achieve optimal balance between reducing parasitic capacitance and maintaining signal integrity, allowing the interconnect structures to function effectively at higher integration densities.
2Quantity of substance
If the geometrical size of interconnect structures is decreased to increase integration density, then the integration density is improved, but manufacturing defects such as voids and kinks increase
Solution Approach 1:
The patent modifies manufacturing parameters including the formation of via holes with specific geometric characteristics, control of film deposition parameters, and adjustment of etching conditions. These parameter changes are optimized to prevent defect formation during manufacturing processes, ensuring high precision fabrication of densely integrated interconnect structures.
Solution Approach 2:
The patent implements preliminary stress relief measures during the manufacturing process, such as forming stress relief openings and applying stress control layers before final interconnect formation. These preliminary actions prevent the development of voids and kinks during subsequent processing steps, maintaining manufacturing precision throughout production.
3Strength
If stress relief measures are implemented to prevent defects, then the mechanical strength is improved, but the manufacturing process complexity increases
Solution Approach 1:
The patent divides the stress relief function into multiple discrete structural elements including stress relief openings, stress control layers, and interface structures. Each element addresses specific stress issues at different locations and depths, providing comprehensive stress management through modular, manageable components that can be integrated into existing manufacturing processes.
Solution Approach 2:
The patent introduces intermediary structures such as stress control layers and stress relief openings that act as mediators between different interconnect layers. These intermediary elements manage stress transfer and distribution, preventing defect formation while maintaining compatibility with standard manufacturing processes and minimizing overall process complexity.
Data Source
AI summary
In order to reduce the incidence of stress concentration areas in an etched opening, a thinner polyimide layer is deposited to minimize gap formation therein, and a descum process is then performed to increase the angle of the presented layer surface. Reduction of the stress in this manner reduces the incidence of cracking of the later formed metal contact, which improves the overall pass rates of semiconductor devices so manufactured.