Semiconductor Structure Via Portion Parasitic Capacitance Reduction
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Solution Overview
Problem
The integration of MEMS devices with CMOS substrates in electronic equipment, such as microphones, leads to high parasitic capacitance, low signal-to-noise ratio, and increased manufacturing complexity, resulting in poor performance and high costs.
Innovation Solution
A semiconductor structure is developed with a conductive substrate having ultra-low resistance, featuring a via portion that reduces parasitic capacitance by electrically connecting the MEMS device to the CMOS substrate through eutectic bonding, thereby minimizing package size and manufacturing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If MEMS devices are integrated with CMOS substrates using conventional methods, then device functionality is achieved, but parasitic capacitance increases and signal-to-noise ratio decreases
Solution Approach 1:
The patent extracts the harmful parasitic capacitance effect by removing the conventional wire bonding interconnection method and replacing it with a direct integrated connection through the substrate. This eliminates the parasitic capacitance generated by external bonding wires and improves the signal-to-noise ratio.
Solution Approach 2:
The patent merges the MEMS device and CMOS substrate into a single integrated structure where the substrate serves as both the mechanical support and the electrical interconnection medium. This integration eliminates the need for separate bonding wires and reduces parasitic capacitance.
2Ease of manufacture
If conventional integration methods are used, then device assembly is achieved, but manufacturing complexity increases
Solution Approach 1:
The patent combines multiple manufacturing processes into a unified integrated fabrication approach. The substrate is designed to provide both mechanical support and electrical interconnection functions, merging what would otherwise be separate assembly steps into a single fabrication process.
Solution Approach 2:
The substrate is designed with multi-functionality, serving as both the mechanical support structure and the electrical interconnection medium. This universal component eliminates the need for separate bonding wires and reduces the overall number of manufacturing steps.
3Volume of moving object
If wire bonding is used for electrical connection, then electrical interconnection is achieved, but package size increases
Solution Approach 1:
The patent removes the external wire bonding structure and replaces it with an integrated substrate-based connection. This extraction of the bonding wire function reduces the overall package size while maintaining electrical interconnection capability through the substrate itself.
Solution Approach 2:
The patent transitions from a three-dimensional wire bonding approach to a planar integrated connection within the substrate. By changing the dimensionality of the electrical interconnection from external wires to internal substrate pathways, the package size is reduced.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances sensitivity, reduces parasitic capacitance, and minimizes the size of the semiconductor structure, leading to improved performance and cost-effectiveness in manufacturing.
Implementation Method 1
The second substrate is conductive, has ultra-low resistance or has a resistivity less than 0.01 ohm-cm
Implementation Method 2
electrically connecting the MEMS device to the CMOS substrate through eutectic bonding
Data Source
AI summary
A semiconductor structure includes a first substrate, a second substrate disposed over the first substrate, and including a first surface, a second surface opposite to the first surface, a via portion extending between the first surface and the second surface, a first through hole and a second through hole, and a device disposed over the second surface, and including a dielectric layer, a backplate at least partially exposed from the dielectric layer and a membrane at least partially exposed from the dielectric layer and disposed between the backplate and the first substrate, wherein the via portion is disposed within the second through hole, and the dielectric layer is bonded with the second substrate, and the device is electrically connected to the first substrate through the via portion.