Semiconductor Power-Line Layout Using Substrate Vias for AOB Buffers
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Solution Overview
Problem
Existing semiconductor devices lack efficient arrangements and connections for buffers with transistors whose sources and drains are directly connected to wirings under the substrate via vias, leading to suboptimal layout and power supply capabilities.
Innovation Solution
The semiconductor device incorporates a specific arrangement of power supply lines, ground lines, and vias that directly connect to the sources and drains of transistors through through-silicon vias (TSVs), allowing for efficient placement of always-on buffers (AOBs) that can supply and stop power supply potentials, thereby optimizing layout and power supply density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If transistors are directly connected to wirings under the substrate via vias, then power supply capability is improved, but layout complexity increases
Solution Approach 1:
The patent utilizes the vertical dimension by forming vias through the substrate to connect power supply lines on the back surface to transistor sources and drains on the front surface. This three-dimensional via-based connection approach resolves the layout complexity issue by enabling direct power delivery without increasing planar layout complexity, thus improving power supply capability while maintaining layout simplicity.
2Productivity
If power supply lines are formed on the back surface of the substrate, then power distribution efficiency is improved, but manufacturing complexity increases
Solution Approach 1:
The patent segments the power supply network into distinct layers: power supply lines are formed on the back surface of the substrate, while transistor elements are formed on the front surface. Through-silicon vias provide vertical interconnection between these segmented layers, enabling efficient power distribution while simplifying manufacturing by allowing independent optimization of front and back surface processing.
Solution Approach 2:
By moving power supply lines to the back surface and using vertical vias for connection, the patent utilizes the third dimension (depth/height) to resolve the conflict between power distribution efficiency and manufacturing complexity. This approach enables efficient power delivery without complicating the manufacturing process, as each surface can be processed independently.
3Quantity of substance
If vias are used to connect transistors to power supply lines, then power supply density is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent optimizes via parameters including diameter, depth, and positioning to achieve high power supply density while maintaining manufacturability. By carefully controlling via dimensions and spacing, the design increases power supply density without excessively raising precision requirements beyond standard semiconductor manufacturing capabilities.
Data Source
AI summary
A semiconductor device includes a substrate, a first power supply line supplied with a first potential, a second power supply line supplied with a second potential, and a third power supply line supplied with a third potential, the first power supply line, the second power supply line, and the third power supply line being formed below the upper surface of the substrate, a first transistor formed above the substrate and arranged at a position overlapping the first power supply line in a plan view, a second transistor formed above the substrate, and a first via formed in the substrate and connected to a source of the first transistor and the first power supply line.