Semiconductor Via Pattern Resizing for Reduced Connection Resistance
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current semiconductor devices face challenges in achieving high reliability and performance due to limitations in integration density and complexity, particularly in the routing and design rules applied to via patterns, which can lead to process failures and performance deterioration.
Innovation Solution
The method involves resizing and differentiating via patterns, specifically the power via patterns, to apply unique design rules, reducing connection resistance and improving electric characteristics by ensuring proper routing and placement of standard cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If via patterns are differentiated with different widths, then connection resistance is reduced and electric characteristics are improved, but device complexity and routing difficulty increase
Solution Approach 1:
The patent applies different width specifications to different via patterns based on their specific functions. Power vias have larger widths to reduce connection resistance and improve electric characteristics, while signal vias maintain standard widths. This local differentiation optimizes electrical performance at critical locations without unnecessarily complicating the entire device structure.
Solution Approach 2:
The via patterns are segmented into different types (power vias and signal vias) with distinct width characteristics. This segmentation allows independent optimization of each via type according to its functional requirements, enabling reduced connection resistance for power connections while maintaining standard routing for signal connections.
2Productivity
If integration density is increased, then device functionality is improved, but manufacturing precision and reliability deteriorate
Solution Approach 1:
By specifying different widths for power vias versus signal vias, the patent creates distinct geometric characteristics that simplify manufacturing precision requirements. Power vias with larger widths are less sensitive to dimensional variations, while signal vias maintain precise but smaller dimensions. This local differentiation allows higher integration density without compromising overall manufacturing precision.
3Reliability
If via pattern widths are differentiated, then connection resistance is reduced, but design rule complexity increases
Solution Approach 1:
The patent changes the width parameter of via patterns based on their functional classification. Power vias are assigned larger width values to reduce connection resistance and improve electrical performance, while signal vias maintain standard width values. This parameter differentiation is implemented through specific design rules that associate width values with via type, managing complexity through systematic parameter assignment rather than arbitrary variations.
Data Source
AI summary
Disclosed are a semiconductor device and a method of fabricating the same. The method includes placing a standard cell, resizing a power via pattern in such a way that the power via pattern has a different width from a width of other via pattern, and applying different design rules to the power via pattern and the other via pattern, respectively, to perform a routing operation on the standard cell.