Semiconductor Via Opening Profile for Stress-Relieved RDL Contacts
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Solution Overview
Problem
As semiconductor technology advances, the decreasing geometrical size of interconnect structures in ICs leads to increased parasitic capacitance and signal delay, cross-talk, and manufacturing defects such as voids and kinks, which weaken the mechanical strength and electrical properties of semiconductor devices.
Innovation Solution
A method is introduced to form semiconductor devices with improved stress relief by forming metal redistribution layers (RDLs) within via holes, using specific interior angles for passivation layers and polyimide openings to reduce stress and prevent defects, including a descum etching process and pull-back operations to enhance the structural integrity of the semiconductor device.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the geometrical size of interconnect structures is decreased to increase integration density, then the integration density is improved, but the parasitic capacitance and signal delay increase
Solution Approach 1:
The patent applies local quality by forming a low-k dielectric layer specifically in the interconnect region where parasitic capacitance is problematic, while maintaining other dielectric layers with different properties in other regions. This localized application of low-k material reduces parasitic capacitance and signal delay in the critical interconnect area without affecting other parts of the device.
Solution Approach 2:
The patent uses composite materials by combining low-k dielectric material with standard dielectric materials in a multi-layer structure. The low-k layer is positioned between metal interconnect lines to reduce capacitance, while other dielectric layers provide mechanical support and electrical isolation, creating a composite structure that addresses both electrical performance and structural requirements.
2Ease of manufacture
If standard manufacturing processes are used for forming interconnect structures, then the manufacturing process is simple, but voids and kinks form that weaken mechanical strength and electrical properties
Solution Approach 1:
The patent applies preliminary action by forming the low-k dielectric layer and performing stress relief etching before completing the interconnect structure fabrication. The stress relief etching creates a tapered profile in advance that prevents void formation during subsequent metal deposition and curing processes, proactively addressing potential defects before they occur.
Solution Approach 2:
The patent converts the potentially harmful stress that causes voids and kinks into a beneficial process by using controlled stress relief etching. The etching process intentionally creates a tapered profile that accommodates stress during curing, transforming what would be a defect-causing stress into a controlled feature that prevents defects.
3Strength
If stress relief measures are implemented to prevent voids and kinks, then the mechanical strength is improved, but the manufacturing process becomes more complex
Solution Approach 1:
The patent uses stress relief etching as an intermediary process between dielectric layer deposition and metal interconnect formation. This intermediate step creates a tapered profile that mediates the stress between layers, preventing voids and kinks without requiring fundamental changes to the overall manufacturing process architecture.
Solution Approach 2:
The patent applies parameter changes by modifying the etching process parameters to create a specific tapered profile in the low-k dielectric layer. By controlling the etch depth and angle, the process achieves stress relief and defect prevention through parameter optimization rather than adding complex process steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the formation of kinks and voids, enhances the mechanical strength, and improves the production yield of semiconductor devices by enlarging the process window without significantly complicating the manufacturing process.
Implementation Method 1
performing a descum etching process to etch a first opening through the polyimide layer
Implementation Method 2
performing a pull-back operation of the polyimide layer to expose a top surface of a second portion of the second passivation layer
Data Source
AI summary
In order to reduce the incidence of stress concentration areas in an etched opening, a thinner polyimide layer is deposited to minimize gap formation therein, and a descum process is then performed to increase the angle of the presented layer surface. Reduction of the stress in this manner reduces the incidence of cracking of the later formed metal contact, which improves the overall pass rates of semiconductor devices so manufactured.