3D Semiconductor Via Layout With Rear Redistribution Layer
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Solution Overview
Problem
Existing three-dimensional semiconductor devices face design restrictions when stacking heterogeneous chips due to alignment challenges of through-silicon vias (TSV) regions.
Innovation Solution
The semiconductor device incorporates a rear redistribution layer and strategically positions rear pads to electrically connect with through-vias, allowing for improved design freedom in TSV region alignment by offsetting or overlapping TSV regions between chips.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If through-silicon vias (TSV) regions of heterogeneous chips are vertically aligned for stacking, then electrical connection is achieved, but design freedom is restricted
Solution Approach 1:
A rear redistribution layer is introduced as an intermediary between the second through-vias and the first through-vias. This layer includes rear pads that can be spaced apart from the second through-vias horizontally while overlapping them vertically, enabling flexible TSV region design without direct alignment requirements between heterogeneous chips
Solution Approach 2:
The patent transitions from two-dimensional horizontal alignment to three-dimensional spatial arrangement by allowing rear pads to overlap through-vias in the vertical direction while being spaced apart horizontally. This dimensional change enables design freedom without compromising electrical connection
2Adaptability or versatility
If TSV regions of stacked chips are offset horizontally, then design freedom is improved, but electrical connection between chips becomes challenging
Solution Approach 1:
The rear redistribution layer serves as a mediator that decouples the alignment relationship between TSV regions of different chips. By introducing rear pads that connect to both the second through-vias (via rear TSVs) and the first through-vias (via bumps), reliable electrical connection is maintained even when TSV regions are horizontally offset
Solution Approach 2:
The electrical connection path is segmented into multiple stages: first through-vias connect to first front pads, which connect to second front pads via bumps, which connect to second through-vias via rear pads, which connect to the rear redistribution layer. This segmentation allows each stage to be independently positioned, enabling horizontal offset between TSV regions while maintaining overall connection reliability
Data Source
Figure 1A~1B
Figure 1C
Figure 2A
AI summary
According to some implementations, provided is a semiconductor device (1000A) including: a first semiconductor chip (C1) including first through-vias (130), and first front pads (104) electrically connected to the first through-vias (130); and a second semiconductor chip (C2) disposed below the first semiconductor chip (C1), and including a substrate (210), a circuit layer (220) disposed below the substrate (210), second front pads (204) below the circuit layer (220), rear pads disposed on the substrate (210) and electrically connected to the corresponding first front pads (104), second through-vias (230) penetrating through the substrate (210) and electrically connected to the second front pads (204), and a rear redistribution layer (140) electrically connecting the second through-vias (230) and the rear pads, wherein at least one of the rear pads is spaced apart from a corresponding one of the second through-vias (230) in a horizontal direction, and overlaps a corresponding one of the first through-vias (130) in a vertical direction.