Semiconductor Via Recess Structure for Delamination Control
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Solution Overview
Problem
As semiconductor devices are scaled down, their operating characteristics deteriorate, leading to challenges in achieving superior performance and reliability due to high integration limitations.
Innovation Solution
The semiconductor device design includes a substrate with an active pattern, channel pattern, source/drain pattern, gate electrode, interlayer dielectric layer with a recess, via, and an adhesion layer between the wiring line and the interlayer dielectric layer, where the via's upper surface is closer to the substrate than the interlayer dielectric layer, and the adhesion layer extends to the inner sidewall of the recess, enhancing electrical connections and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If semiconductor devices are scaled down to improve integration density, then device size is reduced, but operating characteristics deteriorate and reliability decreases
Solution Approach 1:
The adhesion layer is selectively positioned only on the inner sidewall of the recess and not on the upper surface of the via, creating local differentiation in adhesion properties. This local quality enhancement prevents delamination at the critical sidewall interface without creating unintended electrical connections on the via top, thereby improving reliability in scaled-down devices
Solution Approach 2:
The adhesion layer acts as an intermediary between the via structure and the interlayer dielectric layer. By extending this intermediary layer to the inner sidewall of the recess, the patent strengthens the bonding interface and prevents delamination, thus maintaining reliability even as device dimensions are reduced
2Reliability
If adhesion layer is extended to inner sidewall of recess, then delamination is prevented and reliability is improved, but device complexity increases
Solution Approach 1:
The adhesion layer is applied selectively to specific regions (inner sidewall of recess) rather than uniformly across all surfaces. This localized application approach improves reliability where needed while avoiding unnecessary complexity in other areas, as the layer is deliberately omitted from the via upper surface
Solution Approach 2:
Instead of applying the adhesion layer to all surfaces (including via top), the patent inverts the approach by applying it only to the inner sidewall and explicitly excluding it from the via upper surface. This inverted strategy simplifies the overall structure by avoiding unnecessary layers while maintaining reliability
Data Source
AI summary
Disclosed are semiconductor devices and their fabrication methods. The semiconductor device comprises a substrate including an active pattern; a channel pattern on the active pattern; a source/drain pattern electrically connected to the channel pattern; a gate electrode on the channel pattern; an interlayer dielectric layer on the gate electrode, wherein the interlayer dielectric layer includes a recess; a via in the recess; a wiring line on the interlayer dielectric layer and electrically connected to the via; and an adhesion layer between the wiring line and an upper surface of the interlayer dielectric layer, wherein an upper surface of the via is closer than the upper surface of the interlayer dielectric layer to the substrate in a first direction, wherein the first direction is perpendicular to an upper surface of the substrate and wherein a portion of the adhesion layer is on a portion of an inner sidewall of the recess.