3D Semiconductor Via Layout With Rear Redistribution Offset
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Solution Overview
Problem
The design of three-dimensional semiconductor devices with through-silicon vias (TSV) faces challenges in aligning TSV regions of heterogeneous chips, limiting design freedom and efficiency in stacking semiconductor chips.
Innovation Solution
The semiconductor device incorporates a rear redistribution layer that electrically connects second through-vias on a base chip to first through-vias on a stacked chip, allowing for horizontal misalignment while maintaining vertical alignment, thereby enhancing design freedom for the TSV region.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If TSV regions of heterogeneous chips are vertically aligned, then manufacturing precision is improved, but design freedom is limited
Solution Approach 1:
A rear redistribution layer is introduced as an intermediary between the second through-vias in the base chip and the first through-vias in the stacked chip. This redistribution layer enables horizontal offset between TSV regions while maintaining vertical alignment through the intermediary connection, thus resolving the contradiction between alignment precision and design freedom
Solution Approach 2:
The patent separates the alignment function into different dimensions: vertical alignment is maintained for electrical connection through the stacked chips, while horizontal offset is enabled through the rear redistribution layer. This dimensional separation allows TSV regions to be offset in the horizontal plane without compromising vertical alignment requirements
2Adaptability or versatility
If TSV regions are horizontally offset, then design freedom is improved, but manufacturing complexity increases
Solution Approach 1:
The rear redistribution layer serves as a mediator that simplifies the overall device complexity by providing a standardized interface between offset TSV regions. Instead of complex direct alignment requirements, the redistribution layer offers a systematic approach to handling horizontal offsets, making the configuration more manageable
3Adaptability or versatility
If rear pads are spaced apart from second through-vias, then design flexibility is improved, but manufacturing precision requirements increase
Solution Approach 1:
The rear redistribution layer acts as an intermediary between the second through-vias and rear pads, allowing horizontal spacing between them. The redistribution layer provides the necessary electrical connection while accommodating the spatial separation, thus enabling design flexibility without excessive precision requirements for pad-to-via alignment
Data Source
AI summary
According to some implementations, provided is a semiconductor device including: a first semiconductor chip including first through-vias, and first front pads electrically connected to the first through-vias; and a second semiconductor chip disposed below the first semiconductor chip, and including a substrate, a circuit layer disposed below the substrate, second front pads below the circuit layer, rear pads disposed on the substrate and electrically connected to the corresponding first front pads, second through-vias penetrating through the substrate and electrically connected to the second front pads, and a rear redistribution layer electrically connecting the second through-vias and the rear pads, wherein at least one of the rear pads is spaced apart from a corresponding one of the second through-vias in a horizontal direction, and overlaps a corresponding one of the first through-vias in a vertical direction.