Semiconductor Via Resin Adhesion Thermal Stress
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Solution Overview
Problem
Conventional semiconductor devices experience adhesion issues between sealing resin and resist layers due to thermal expansion differences, leading to stress concentration and separation, and warping caused by different physical properties of materials, resulting in connectivity issues during mounting.
Innovation Solution
A semiconductor device with a wiring board featuring vias filled with a resin of different physical properties, where the resist layer is opened over the vias to allow direct adhesion of the sealing resin, and grooves in the resist layer facilitate even resin distribution, preventing stress concentration and warping.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If vias are filled with via filling resin having different physical properties from sealing resin, then electrical connectivity is achieved, but stress concentration occurs at the via periphery due to thermal expansion differences
Solution Approach 1:
The patent changes the physical parameters of the sealing resin by selecting a material whose coefficient of thermal expansion closely matches that of the via filling resin. This parameter matching reduces thermal expansion differences and eliminates stress concentration at the via periphery during temperature cycles.
Solution Approach 2:
The patent uses a composite structure where the sealing resin and via filling resin are selected to have compatible physical properties. This composite material approach ensures that both materials expand and contract at similar rates, preventing delamination and stress concentration while maintaining electrical connectivity through the via filling resin.
2Stability of the object's composition
If resist layer covers the via completely, then wiring board structure is maintained, but adhesion between sealing resin and resist layer deteriorates due to stress concentration
Solution Approach 1:
The patent changes the adhesion parameters by selecting a sealing resin that forms strong adhesive bonds with the resist layer despite the presence of vias. The sealing resin is specifically chosen to maintain high adhesion strength even when the resist layer covers the via, preventing delamination during thermal cycling.
3Adaptability or versatility
If different materials with different physical properties are used in the semiconductor device, then functional requirements are met, but warping occurs due to differential thermal expansion
Solution Approach 1:
The patent changes the thermal expansion parameters of the materials used in the semiconductor device. By selecting a sealing resin whose coefficient of thermal expansion matches that of the via filling resin and wiring board, the patent minimizes differential thermal expansion and prevents warping while still meeting functional requirements for electrical connectivity and sealing.
4Reliability
If via filling resin with high coefficient of thermal expansion is used, then via electrical connectivity is ensured, but adhesion to sealing resin decreases due to thermal stress
Solution Approach 1:
The patent changes the thermal expansion parameter of the via filling resin by selecting a material with a coefficient of thermal expansion that closely matches the sealing resin. This parameter matching ensures both electrical connectivity through the via and strong adhesion to the sealing resin, eliminating the trade-off between connectivity and adhesion strength.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enhances adhesion between sealing resin and via filling resin, reduces stress concentration, and prevents warping, ensuring reliable connectivity and structural integrity during mounting.
Implementation Method 1
the via filling resin 12 with which the vias 13 are filled expands in the assembling time of the semiconductor device 10 or its heating process for packaging, and contracts after cooling
Data Source
AI summary
A semiconductor device is disclosed that includes a wiring board having a via formed therein; a semiconductor element provided on the wiring board; a resist layer covering a surface of the wiring board, the resist layer having an opening in a part thereof positioned on the via; and a sealing resin covering the surface of the via in the opening and the resist layer, and sealing the semiconductor device.


