Semiconductor Via Heat Dissipation via Resist Barrier
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Solution Overview
Problem
Semiconductor integrated circuit devices face challenges in heat dissipation due to miniaturization, where the small surface area restricts surface heat dissipation, and the lateral heat dissipation performance is compromised by substrate thinning, necessitating effective vertical heat dissipation paths through vias, but existing via configurations can lead to solder suction and electric short-circuits.
Innovation Solution
A semiconductor integrated circuit device design featuring an insulating substrate with a via penetrating through, a metal layer on the substrate, a resist layer, and a solder layer with a gap region formed between the solder and resist layers, allowing for improved heat dissipation without solder suction, achieved by a reflow process that fuses the solder only to the metal layer, preventing flow into the via.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Temperature
If a via is present to enable vertical heat dissipation, then heat dissipation performance is improved, but solder suction and electric short-circuits occur
Solution Approach 1:
A resist layer is introduced as an intermediary substance filling the via hole between the insulating substrate and the solder layer. This resist layer acts as a physical barrier that prevents solder from being sucked into the via during the reflow process, while still allowing thermal conduction to occur through the via structure for heat dissipation.
Solution Approach 2:
The via hole is filled with resist material before the solder layer is applied. This preliminary action of filling the via with resist prevents the subsequent problem of solder suction into the via during reflow, eliminating the need for post-process repairs and ensuring reliable electrical isolation.
2Quantity of substance
If the insulating substrate is thinned to reduce cost, then substrate cost is reduced, but lateral heat dissipation performance is restricted
Solution Approach 1:
The patent transitions heat dissipation from primarily lateral conduction through the substrate to vertical conduction through the via holes. By utilizing the vertical dimension via through-holes filled with thermally conductive resist material, effective heat dissipation is achieved even in thinned substrates where lateral heat paths are limited.
3Area of moving object
If the surface area is reduced due to miniaturization, then device size is reduced, but surface heat dissipation capability is insufficient
Solution Approach 1:
The patent moves heat dissipation from the surface plane to the vertical dimension by implementing through-substrate via holes. This allows heat to escape through the thickness of the substrate via vertical conduction paths, compensating for the reduced surface area available for heat dissipation in miniaturized devices.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enhances heat dissipation performance by preventing solder suction and electric short-circuits, maintaining high solder fusion rates and ensuring reliable heat transfer through the via, thus reducing thermal resistance and maintaining the integrity of the semiconductor integrated circuit device.
Implementation Method 1
performing a reflow process to form a gap region between the solder layer and the first resist layer while fusing the solder layer and the first metal layer
Implementation Method 2
heat dissipation from the substrate is predominant... heat dissipation performance in the lateral direction of the substrate is restricted... the existence of a through-hole or a via which realizes a heat dissipation path in the vertical direction affects the heat dissipation performance
Data Source
AI summary
A semiconductor integrated circuit device includes: an insulating substrate; a via which penetrates through the insulating substrate; a first metal layer disposed on a front surface of the insulating substrate; a first resist layer disposed on the first metal layer in the vicinity of the via; a solder layer disposed on the first metal layer, the via and the first resist layer; a gap region formed between the solder layer and the first resist layer, and a semiconductor integrated circuit disposed on the solder layer.