Semiconductor Interconnect Via Structure for Lower Resistance Etching
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Solution Overview
Problem
The increasing integration of semiconductor devices leads to challenges in reducing the resistance of interconnection layers and vias while maintaining electrical characteristics and reliability, particularly due to the reduction in size and capacitance between these components.
Innovation Solution
The semiconductor device incorporates a design with inclined side surfaces in interconnection layers and vias, utilizing different metals for each layer, and is formed through specific etching processes to enhance electrical connectivity and reliability, avoiding the need for etch stop layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the size of interconnection layers and vias is reduced to increase integration, then the degree of integration is improved, but the resistance of interconnection layers and vias increases
Solution Approach 1:
The patent changes the physical parameters of the vias by creating inclined side surfaces instead of vertical walls, and uses different metals for different layers. The inclined geometry changes the effective cross-sectional area and current distribution, while the material composition changes (different metals for different via layers) optimize electrical conductivity to reduce resistance despite reduced dimensions.
Solution Approach 2:
The patent employs composite material structures by using different metals for different via layers (e.g., copper for upper via, aluminum for lower via). This composite approach allows optimization of each layer's material properties to minimize overall resistance while maintaining the reduced size required for high integration.
2Productivity
If the size of interconnection layers and vias is reduced to increase integration, then the degree of integration is improved, but the capacitance between interconnection layers decreases
Solution Approach 1:
The inclined side surfaces of the vias change the geometric parameters of the interconnection structure, increasing the surface area available for capacitive coupling between layers while maintaining compact overall dimensions. This geometric parameter change helps maintain capacitance despite size reduction.
3Ease of manufacture
If conventional etching processes are used, then manufacturing is simpler, but damage occurs during etching requiring etch stop layers
Solution Approach 1:
The patent changes the geometry parameter of the via holes from vertical to inclined side surfaces. This inclination angle parameter change modifies the etching dynamics, allowing the etch front to progress more uniformly and reducing lateral damage to surrounding structures, thereby eliminating the need for additional etch stop layers.
Data Source
AI summary
A semiconductor device includes a lower structure including a substrate, a first interconnection layer extending in a first direction on the lower structure, and including a first metal, a first via contacting a portion of an upper surface of the first interconnection layer and including a second metal, a second via contacting at least a portion of an upper surface of the first via and having a maximum width narrower than a maximum width of the first via, and a second interconnection layer connected to the second via and extending in a second direction. The first interconnection layer has inclined side surfaces in which a width of the first interconnection layer becomes narrower towards an upper region of the first interconnection layer, and the first via has inclined side surfaces in which a width of the first via becomes narrower towards an upper region of the first via.