Semiconductor Metal-Layer Layout With Vertical Via Routing
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Solution Overview
Problem
Current semiconductor device layouts face challenges in efficiently connecting conductors across different metal layers while minimizing area, power consumption, and capacitance, often requiring circuitous routes that increase complexity and resource usage.
Innovation Solution
The solution involves forming conductors in the M0 metal layer parallel to the X-axis and connecting them with conductors in the M1 metal layer parallel to the Y-axis using conductive vias, allowing for direct and efficient connections without the need for circuitous paths, thereby reducing area and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If conductors in adjacent metal layers are connected using conventional routing methods, then connectivity between layers is achieved, but the routing paths become circuitous and increase area consumption
Solution Approach 1:
The patent applies dimensionality change by transitioning from planar 2D routing to 3D vertical routing through the introduction of conductive vias. Conductors in the first metal layer connected to conductors in the second metal layer via vertical vias, enabling direct three-dimensional connections that eliminate circuitous two-dimensional paths, thereby reducing area consumption and routing complexity simultaneously.
2Use of energy by moving object
If conductors are connected across different metal layers with conventional paths, then layer connectivity is established, but power consumption increases due to longer routing paths
Solution Approach 1:
The patent reduces power consumption by enabling direct vertical connections through conductive vias between metal layers. This three-dimensional routing approach shortens the electrical path length compared to conventional planar routing, thereby reducing resistive power losses while improving routing efficiency and signal integrity.
3Object-generated harmful factors
If conventional routing methods are used to connect conductors in adjacent layers, then connectivity is achieved, but parasitic capacitance increases
Solution Approach 1:
The patent reduces parasitic capacitance by implementing direct vertical connections through conductive vias between adjacent metal layers. This three-dimensional routing approach minimizes the horizontal trace length and associated capacitive coupling between adjacent conductors, thereby reducing parasitic effects and improving signal integrity and electrical performance.
4Area of stationary object
If pitch is increased to accommodate routing connections between metal layers, then connectivity is achieved, but device compactness is reduced
Solution Approach 1:
The patent maintains device compactness by utilizing vertical vias for inter-layer connections, which occupy minimal horizontal space. This three-dimensional routing approach allows pitch to be determined by standard design rules without requiring increased spacing for routing maneuvers, thereby preserving device compactness while achieving reliable connectivity between metal layers.
Data Source
AI summary
A semiconductor device, includes a first metal layer, a second metal layer, a drain/source contact and at least one conductive via. The first metal layer has a first conductor that extends in a first direction and a second conductor that extends in the first direction, wherein the second conductor is directly adjacent to the first conductor. The second metal layer has a third conductor that extends in a second direction, wherein the second direction is transverse to the first direction. The drain/source contact extends in the second direction and is connected to the second conductor. The at least one conductive via connects the first conductor and the second conductor through the third conductor.