Semiconductor Via Structure for Uniform Seed Layer Deposition
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Solution Overview
Problem
As semiconductor devices shrink in size, maintaining reliable electrical quality of conductive elements becomes increasingly challenging due to the complexity and difficulty of fabrication processes, particularly in forming uniform seed layers within narrow holes.
Innovation Solution
The process involves forming enlarged and neck portions in holes within the semiconductor device structure to improve step coverage uniformity of seed layers, using a sputtering process to deposit conductive materials, and subsequently forming wiring layers that are electrically connected through these seed layers, enhancing the electrical connection properties between layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If feature sizes continue to decrease to increase functional density, then production efficiency increases and costs decrease, but fabrication process difficulty increases and electrical quality of conductive elements deteriorates
Solution Approach 1:
The patent segments the hole structure into three distinct portions (first enlarged portion, neck portion, and second enlarged portion) with different geometries. This segmentation allows each portion to be optimized independently for its specific function: the enlarged portions facilitate uniform seed layer deposition while the neck portion provides mechanical support and electrical connection, thereby resolving the contradiction between miniaturization and manufacturing precision.
Solution Approach 2:
The patent applies local quality by giving different geometric characteristics to different portions of the hole structure. The first and second enlarged portions have larger cross-sectional areas to accommodate uniform seed layer deposition, while the neck portion has a smaller cross-sectional area for structural support. This localized differentiation enables the structure to maintain electrical quality despite overall size reduction.
2Volume of moving object
If conventional hole structures are used in miniaturized devices, then device size decreases, but step coverage uniformity of seed layers deteriorates
Solution Approach 1:
The hole is divided into three segments with varying cross-sectional areas. The first enlarged portion (closer to the top surface) and second enlarged portion (closer to the bottom surface) provide sufficient space for uniform seed layer deposition from both directions, while the neck portion in the middle provides structural support. This segmentation resolves the step coverage issue while maintaining miniaturization.
Solution Approach 2:
The patent transitions from a simple cylindrical hole to a three-dimensional hourglass-shaped structure with varying cross-sectional areas along the depth dimension. This dimensional change allows the structure to accommodate uniform seed layer deposition requirements while maintaining overall device miniaturization.
3Area of stationary object
If feature sizes are reduced to increase functional density, then chip area utilization improves, but fabrication process complexity increases
Solution Approach 1:
The patent employs preliminary action by forming the complex hourglass-shaped hole structure with pre-defined enlarged portions and neck portions before seed layer deposition. This preliminary structuring ensures that subsequent seed layer deposition processes can proceed uniformly without requiring complex real-time adjustments, thereby reducing overall fabrication complexity despite the intricate hole geometry.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves the performance of semiconductor devices by ensuring uniform deposition of seed layers and enhancing the electrical connection between wiring layers, thereby addressing the reliability issues at smaller scales.
Implementation Method 1
using a sputtering process to deposit conductive materials
Data Source
AI summary
A method for forming a semiconductor device structure is provided. The method includes providing a chip structure including a substrate and a wiring structure over a first surface of the substrate. The method includes removing a first portion of the wiring structure adjacent to the hole to widen a second portion of the hole in the wiring structure. The second portion has a first width increasing in a first direction away from the substrate. The method includes forming a first seed layer over the wiring structure and in the hole. The method includes thinning the substrate from a second surface of the substrate until the first seed layer in the hole is exposed. The method includes forming a second seed layer over the second surface of the substrate and the first seed layer in the hole.