Semiconductor Via Structure for Uniform Seed Layer Coverage
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Solution Overview
Problem
The challenge in the semiconductor industry is to maintain reliable semiconductor devices at increasingly smaller sizes due to the difficulty in forming conductive elements with acceptable electrical quality, as feature sizes decrease and fabrication processes become more complex.
Innovation Solution
The process involves forming semiconductor device structures with enlarged portions and neck portions in holes to improve step coverage uniformity of seed layers, allowing for better electrical connections between wiring layers, which includes widening hole openings, depositing seed layers, and thinning substrates to ensure uniform deposition of conductive materials.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If feature sizes are decreased to increase functional density, then production efficiency is improved and costs are lowered, but fabrication process complexity increases and electrical quality of conductive elements deteriorates
Solution Approach 1:
The patent applies local quality by creating enlarged portions at specific locations within holes (at the first surface and second surface) while maintaining a narrower neck portion in between. This localized variation in hole geometry allows for improved seed layer deposition and electrical connection quality at critical interfaces without requiring all holes to be larger overall, thus maintaining productivity while improving manufacturing precision for conductive elements.
Solution Approach 2:
The patent introduces a dimensional variation along the depth of the holes by creating enlarged portions at the top and bottom surfaces with a constricted neck in between. This transforms a simple cylindrical hole into a complex three-dimensional structure with varying cross-sectional areas, enabling better step coverage and electrical connectivity without increasing the overall lateral footprint, thereby maintaining production efficiency while improving electrical quality.
2Area of stationary object
If feature sizes are decreased to increase functional density, then chip area is reduced, but fabrication process difficulty increases
Solution Approach 1:
The patent applies local quality by creating enlarged portions at specific locations within holes (at the first surface and second surface) while maintaining a narrower neck portion in between. This localized variation in hole geometry allows for improved seed layer deposition and electrical connection quality at critical interfaces without requiring all holes to be larger overall, thus maintaining productivity while improving manufacturing precision for conductive elements.
Solution Approach 2:
The patent employs preliminary action by forming the enlarged portions and neck portions in the holes before depositing the seed layers and conductive materials. This pre-structured geometry ensures that subsequent deposition processes achieve uniform step coverage and reliable electrical connections, reducing fabrication difficulties and improving manufacturing ease for small-scale devices.
3Manufacturing precision
If hole openings are widened to improve step coverage uniformity, then manufacturing complexity increases, but seed layer deposition quality improves
Solution Approach 1:
The patent applies segmentation by dividing the hole structure into distinct segments: enlarged portions at the top and bottom surfaces, and a neck portion in between. This segmentation allows each region to serve a specific function - the enlarged portions provide better step coverage for seed layer deposition, while the neck portion maintains electrical connectivity. The segmented structure achieves improved manufacturing precision without requiring the entire hole to be complex.
Solution Approach 2:
The patent applies local quality by creating enlarged portions at specific locations within holes (at the first surface and second surface) while maintaining a narrower neck portion in between. This localized variation in hole geometry allows for improved seed layer deposition and electrical connection quality at critical interfaces without requiring all holes to be larger overall, thus maintaining productivity while improving manufacturing precision for conductive elements.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the electrical connection properties between wiring layers, improving the performance and reliability of semiconductor devices by ensuring uniform coverage and connectivity, even at smaller scales.
Implementation Method 1
depositing a first seed layer over the wiring structure and in the hole
Implementation Method 2
depositing a first seed layer over the wiring structure and in the hole
Data Source
AI summary
A semiconductor device structure is provided. The semiconductor device structure includes a chip structure including a substrate and a wiring structure over a first surface of the substrate. The semiconductor device structure includes a first seed layer over the wiring structure, a first inner wall of the first enlarged portion, and a second inner wall of the neck portion. The semiconductor device structure includes a second seed layer over a second surface of the substrate, a third inner wall of the second enlarged portion, and the first seed layer over the second inner wall of the neck portion. The second seed layer is in direct contact with the first seed layer.