Semiconductor Device Via Segmentation for Etching Yield
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Solution Overview
Problem
As semiconductor devices miniaturize, the high aspect ratio of through vias (TSVs) in silicon substrates makes etching processing more difficult, leading to reliability issues such as faulty connections and operational malfunctions, and reduces yield due to the dishing effect during chemical mechanical polishing (CMP) processes.
Innovation Solution
A semiconductor device structure is implemented with multiple conductive regions, including a first via that pierces the substrate and a second via that stops within the semiconductor region, along with an insulating film, to prevent open faults and ensure reliable connections, and the use of a thin semiconductor layer formed by grinding reduces the aspect ratio of via holes, making etching more manageable.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If through vias are formed deep in the semiconductor substrate to enable high-density mounting, then high-speed data transfer is enabled, but the aspect ratio becomes higher and etching processing becomes more difficult
Solution Approach 1:
The patent divides the single deep through via into multiple shallower via holes arranged in an array. Each via hole has a smaller depth and lower aspect ratio, making etching processing easier while collectively achieving the same electrical connection function through parallel pathways.
Solution Approach 2:
The patent transitions from a single vertical via structure to a two-dimensional array of multiple vias. This dimensional change allows the system to achieve equivalent electrical connectivity through distributed shallower holes rather than one deep hole, reducing the aspect ratio of individual via structures.
2Quantity of substance
If through vias are formed deep in the semiconductor substrate, then high-density mounting is enabled, but reliability is reduced due to faulty connections
Solution Approach 1:
The patent segments the single deep via connection into multiple parallel via connections. This segmentation provides redundant electrical pathways, so if one via fails, others can maintain the connection, thereby improving reliability while maintaining high-density mounting capability.
Solution Approach 2:
The patent incorporates multiple via holes as a preventive measure against connection failures. By providing redundant pathways before faults occur, the system cushions against potential reliability issues that would affect single-deep via structures.
3Reliability
If via holes are formed deep in the semiconductor substrate, then electrical connection is achieved, but yield is reduced due to operational malfunctions
Solution Approach 1:
The patent uses multiple shallower via holes instead of one deep via, reducing the difficulty of precise formation and improving manufacturing yield. The segmented structure is more tolerant of fabrication variations while achieving the same electrical connection reliability.
Solution Approach 2:
The patent changes the depth parameter of individual via holes from deep to shallow, and compensates by increasing the number of via holes. This parameter change makes etching processing more controllable and improves manufacturing yield while maintaining electrical connection reliability.
4Ease of manufacture
If the semiconductor layer is made thin to reduce aspect ratio, then etching becomes more manageable, but the via holes may not reach the intended depth
Solution Approach 1:
The patent segments the depth requirement across multiple via holes rather than requiring one via to traverse the entire thin semiconductor layer. Each via hole only needs to reach a local target, improving depth precision control during manufacturing.
Solution Approach 2:
The patent uses multiple via holes that may individually stop before reaching the full depth, but collectively provide sufficient electrical connection. This partial action approach tolerates variations in individual via depth while achieving the overall manufacturing goal.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This structure prevents open faults between through vias and electrodes, stabilizes electric potential, and reduces the likelihood of operational malfunctions and yield reduction, allowing for stable operation and higher reliability even when via holes do not reach the intended depth.
Implementation Method 1
a pn junction is formed between the semiconductor layer and the semiconductor region
Implementation Method 2
an insulating film, and provided between the conductive region and the semiconductor region
Data Source
AI summary
According to one embodiment, a semiconductor device includes: a semiconductor substrate, the semiconductor substrate having first and second surfaces; conductive regions extending in a direction from the first surface side toward the second surface side of the semiconductor substrate, the conductive regions including first and second vias; a first semiconductor region surrounding a part of each of the conductive regions on the second surface side of the semiconductor substrate, a portion other than a front surface of the first semiconductor region being surrounded by the semiconductor substrate; a first electrode provided on the second surface side; second electrodes provided on the first surface side, one of the second electrodes being in contact with one of the conductive regions; and an insulating film provided between each of the conductive regions and the semiconductor substrate, and between each of the conductive regions and the first semiconductor region.