Semiconductor Device Via Segmentation for Parasitic Reduction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Semiconductor devices with three-dimensional integrated circuits face significant parasitic issues such as RC delay and parasitic capacitance due to long via members connecting elements across different layers, which negatively impact device performance.
Innovation Solution
A semiconductor device design where two separated horizontal conductive members are electrically connected through a single vertical conductive member, utilizing a copper or tungsten portion with a diffusion barrier and etch-stop layers, to minimize parasitic effects by reducing the length of the vertical connection within the dielectric layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If via members extend through separated vias to connect different layers, then electrical connectivity between layers is achieved, but parasitic capacitance and RC delay increase significantly
Solution Approach 1:
The patent transitions from traditional vertical via connections to a planar conductor configuration. The conductor extends laterally between contact holes in the same or adjacent layers, changing the connection dimension from vertical to horizontal/planar, thereby reducing parasitic effects associated with long vertical vias
Solution Approach 2:
The conductive path is segmented into multiple portions (first conductor portion, second conductor portion, third conductor portion) that can be positioned in different layers and connected through contact holes. This segmentation allows optimization of each segment's position to minimize overall parasitic capacitance while maintaining connectivity
2Reliability
If long via members are used to connect separated vias, then electrical connection between different layers is established, but RC delay increases
Solution Approach 1:
The invention replaces long vertical via connections with shorter lateral conductor segments. By changing the connection geometry from vertical extension to lateral extension with intermediate contacts, the effective resistance and capacitance are reduced, thereby decreasing RC delay
Solution Approach 2:
The patent introduces intermediate contact holes and conductor portions that act as mediators to connect different layers. Instead of a single long via, multiple shorter conductor segments are connected through intermediate contacts, reducing the overall RC delay of the interconnection path
Data Source
AI summary
A semiconductor device may include the following elements: a first substrate; a second substrate; a dielectric layer, which may be positioned between the first substrate and the second substrate and may have a hole; a first conductive member, which may be positioned in the dielectric layer; a second conductive member, which may be positioned in the dielectric layer, may be spaced from the first conductive member, and may be positioned closer to the second substrate than the first conductive member; and a third conductive member, which may contact both the first conductive member and the second conductive member through the hole.