Semiconductor Via Fabrication Using One Mask for Multiple Sizes
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The semiconductor industry faces challenges in manufacturing semiconductor structures with vias of different dimensions, which increases manufacturing complexity and costs.
Innovation Solution
A method of manufacturing a semiconductor structure involving the use of a mask with different transmission rates during lithography to form vias of varying sizes, allowing for the creation of semiconductor structures with at least two vias of different sizes using a single mask.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If multiple masks are used to form vias of different sizes, then via dimension precision is improved, but device complexity and manufacturing cost increase
Solution Approach 1:
The mask is designed with spatially varying transmission rates, where different regions of the mask have different optical properties. The first region has a first transmission rate and the second region has a second transmission rate, allowing different via sizes to be formed in different locations simultaneously during a single lithography exposure process.
Solution Approach 2:
The mask transmission rate parameter is varied across different regions of the mask. By changing the transmission rate parameter from a uniform value to a spatially varying value, the patent enables the formation of vias with different dimensions using a single mask and single exposure process, thereby reducing manufacturing complexity while maintaining via dimension precision.
2Manufacturing precision
If multiple lithography processes are used to form vias of different sizes, then via dimension precision is improved, but manufacturing time and productivity are reduced
Solution Approach 1:
The patent combines multiple lithography functions into a single mask and single exposure process. Instead of performing separate lithography processes for forming vias of different sizes, the merged approach uses one mask with multiple transmission rate regions to simultaneously define all via patterns, thereby improving manufacturing throughput while maintaining via dimension precision.
Solution Approach 2:
The mask is designed to perform multiple functions simultaneously: it defines the positions, sizes, and patterns of vias with different dimensions in a single exposure. This multi-functional mask replaces what would traditionally require multiple specialized masks and multiple lithography steps, thereby improving productivity without sacrificing via dimension precision.
3Manufacturing precision
If multiple masks are used to form vias of different sizes, then via dimension precision is improved, but manufacturing cost increases
Solution Approach 1:
The patent merges the functions of multiple masks into a single mask structure. By combining what would traditionally require multiple separate masks into one multi-region mask with varying transmission rates, the manufacturing cost is reduced while the via dimension precision is maintained through the different transmission rate regions.
4Device complexity
If a single mask is used to form vias of different sizes, then manufacturing complexity is reduced, but via dimension precision may deteriorate
Solution Approach 1:
The mask is designed with spatially varying transmission rates, where different regions of the mask have different optical properties. The first region has a first transmission rate and the second region has a second transmission rate, allowing different via sizes to be formed in different locations simultaneously during a single lithography exposure process.
Solution Approach 2:
The mask transmission rate parameter is varied across different regions of the mask. By changing the transmission rate parameter from a uniform value to a spatially varying value, the patent enables the formation of vias with different dimensions using a single mask and single exposure process, thereby reducing manufacturing complexity while maintaining via dimension precision.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces manufacturing costs and materials by enabling the formation of multiple via sizes using a single mask, thereby simplifying the manufacturing process.
Implementation Method 1
The fabrication of semiconductor devices involves sequentially depositing various material layers over a semiconductor wafer, and patterning the material layers using lithography and etching processes
Implementation Method 2
A method of manufacturing a semiconductor structure involving the use of a mask with different transmission rates during lithography to form vias of varying sizes
Data Source
AI summary
The present application provides a method of manufacturing a semiconductor structure having vias with different dimensions and a manufacturing method of the semiconductor structure. The method includes: providing a first wafer including a first substrate, a first dielectric layer over the first substrate, and a first conductive pad surrounded by the first dielectric layer; providing a second wafer including a second dielectric layer, a second substrate over the second dielectric layer, and a second conductive pad surrounded by the second dielectric layer; forming a passivation over the second substrate; forming a first conductive via extending from the first conductive pad through the second wafer and the passivation, and having a first width surrounded by the second wafer; and forming a second conductive via extending from the second conductive pad through the passivation and the second substrate and partially through the second dielectric layer, and having a second width surrounded by the second wafer.