3D Stacked Semiconductor Structure With Through-Molding Via
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Solution Overview
Problem
The miniaturization of semiconductor devices leads to increased complexity in manufacturing, resulting in issues such as poor electrical interconnection and delamination, which can cause high yield loss and suboptimal performance due to challenges in electrical communication speed and heat dissipation.
Innovation Solution
A semiconductor structure is designed with a first die over an interconnect structure, surrounded by a molding, and a second die disposed over the molding with a via extending through to electrically connect the two, minimizing routing and enhancing communication speed while reducing power consumption and overall dimensions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If the semiconductor device is miniaturized to reduce size, then the device dimension is reduced, but the manufacturing complexity increases and electrical interconnection quality deteriorates
Solution Approach 1:
The patent transitions from planar routing to three-dimensional vertical routing by stacking dies and using through-molding vias. This dimensional change allows electrical connections to be established vertically through the molding compound rather than requiring complex lateral routing, thereby reducing manufacturing complexity while maintaining miniaturization benefits
Solution Approach 2:
The patent embeds conductive vias within the molding compound that surround and connect multiple stacked dies. The via structure is nested within the molding material, creating an integrated three-dimensional interconnection system that simplifies the overall manufacturing process while enabling compact device architecture
2Adaptability or versatility
If more manufacturing operations are implemented in miniaturized scale, then device functionality increases, but electrical interconnection quality and component reliability deteriorate
Solution Approach 1:
By moving to vertical three-dimensional routing through stacked dies and through-molding vias, the patent simplifies the interconnection architecture. This dimensional transition reduces the number of manufacturing operations required while improving electrical connection reliability through direct vertical pathways that are less susceptible to manufacturing defects
Solution Approach 2:
The molding compound serves as an intermediary medium that houses and protects the conductive vias connecting stacked dies. This intermediary structure provides mechanical support and electrical isolation, enhancing connection reliability while enabling complex multi-die functionality
3Ease of manufacture
If traditional routing methods are used in miniaturized devices, then manufacturing is simpler, but electrical communication speed decreases and power consumption increases
Solution Approach 1:
The patent implements vertical three-dimensional routing through stacked dies and through-molding vias, creating direct electrical pathways that significantly shorten signal transmission distances compared to traditional lateral routing. This dimensional change dramatically increases electrical communication speed while the self-aligned via formation process maintains manufacturing simplicity
Data Source
AI summary
A semiconductor structure includes a first die, a molding at least partially surrounding the first die, a via extended through the molding, a second die disposed over the molding, a connector dispose between the second die and the via, and an underfill at least partially surrounding the connector. The first die includes a first surface and a second surface opposite to the first surface. The second die includes a third surface facing the first die, a fourth surface opposite to the third surface, and a sidewall between the third surface and the fourth surface. The connector is in contact with the third surface of the second die and the via. The second die is electrically connected to the via. The underfill covers a portion of the sidewall of the second die and a portion of the second surface of the first die.