Semiconductor Device Via Terminal Positioning
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In semiconductor devices, the length of wiring between through vias and external terminals is typically long, leading to increased wiring resistance and capacitance, which results in signal delay and timing gaps between signals.
Innovation Solution
The semiconductor device design includes a configuration where intermediate terminals are positioned closer to the center axis than external terminals, and through vias are positioned even closer, reducing the wiring length and thereby minimizing wiring resistance and capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If through vias are connected to external terminals via conventional wiring paths, then electrical connection is established, but wiring length becomes long leading to increased wiring resistance and capacitance
Solution Approach 1:
The patent repositions intermediate terminals from the conventional peripheral arrangement to a location closer to the center axis of the substrate. This spatial reconfiguration in the radial dimension reduces the wiring path length between through vias and external terminals, thereby decreasing wiring resistance and capacitance while maintaining electrical connectivity.
Solution Approach 2:
The patent applies different spatial positioning strategies to different terminals: intermediate terminals are positioned closer to the center axis to minimize wiring length for through via connections, while external terminals maintain their functional positioning. This localized optimization reduces wiring resistance and capacitance specifically for critical signal paths without compromising overall device functionality.
2Reliability
If wiring length between through vias and external terminals is long, then electrical connection is established, but signal delay and timing gaps increase
Solution Approach 1:
By repositioning intermediate terminals closer to the center axis, the patent reduces the radial distance that signals must travel. This dimensional optimization directly decreases signal propagation time and reduces timing gaps between signals while maintaining reliable signal transmission through the stacked semiconductor chips.
3Length of stationary object
If intermediate terminals are positioned closer to center axis, then wiring length is reduced, but terminal arrangement complexity increases
Solution Approach 1:
The patent implements selective repositioning where only intermediate terminals (which connect through vias to upper chips) are moved closer to the center axis, while external terminals remain in their conventional peripheral positions. This localized structural modification reduces wiring length for critical internal connections without significantly increasing overall device complexity or compromising external connectivity.
Data Source
AI summary
A semiconductor device includes a first chip having a through via, a second chip having a first terminal that is electrically connected to the through via, and a substrate having a second terminal disposed on a first surface thereof and electrically connected to the first terminal. When viewed along a straight line that intersects a center axis that is perpendicular to the first surface and intersects a center point of the substrate, the first terminal is disposed further towards the center axis than the second terminal and the through via is disposed further towards the center axis than the first terminal.