Stack Type Semiconductor Device Via Testing Without Back-Grinding
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Solution Overview
Problem
Existing stack type semiconductor devices face challenges in testing vias without damaging the wafer, as back-grinding for via exposure can lead to cracking and pattern removal issues, and Boundary Scan Test methods are inadequate for precise screening of bad vias, resulting in yield and reliability concerns.
Innovation Solution
A semiconductor device and method that includes a semiconductor substrate with a via array and bias pad, allowing for pre-back-grinding testing by forming specific doping regions and wells, enabling via and core tests without exposing the substrate, thus preventing damage and ensuring only good dies are stacked and packaged.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If back-grinding is performed to expose vias for testing, then via testing becomes possible, but the wafer may crack or roll due to thinning
Solution Approach 1:
The patent applies preliminary action by forming test patterns and performing via tests on the front surface of the wafer before back-grinding is performed. This allows via testing to be completed while the wafer still has sufficient thickness and structural integrity, eliminating the need to expose vias through back-grinding just for testing purposes.
Solution Approach 2:
The patent inverts the conventional testing approach by performing via tests on the front surface of the wafer rather than on the back surface. Instead of exposing vias through back-grinding and testing from the back, the invention routes test signals through the substrate to access vias from the front, thereby maintaining wafer strength while enabling testing.
2Measurement precision
If specific patterns are formed in the back of the semiconductor substrate for testing, then via testing is enabled, but additional process steps and potential damage occur
Solution Approach 1:
The patent applies preliminary action by forming test patterns and performing via tests on the front surface of the wafer before back-grinding is performed. This allows via testing to be completed while the wafer still has sufficient thickness and structural integrity, eliminating the need to expose vias through back-grinding just for testing purposes.
Solution Approach 2:
The patent uses the front surface test patterns to serve multiple functions: testing vias, testing core circuit patterns, and providing electrical connections. This multi-functional approach eliminates the need for separate back-surface test patterns and subsequent removal processes, reducing overall process complexity.
3Ease of operation
If Boundary Scan Test method is used after stacking dies, then testing can be performed, but bad vias cannot be precisely screened
Solution Approach 1:
The patent applies preliminary action by performing via tests on individual dies at the wafer level before the dies are stacked and packaged. This preliminary screening identifies and isolates dies with bad vias, ensuring that only good dies proceed to stacking. This approach provides precise via screening that Boundary Scan Test cannot achieve after stacking.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables effective screening of vias at the wafer level before packaging, improving yield and reliability by preventing electrical interference and allowing for selective via testing without back-grinding, ensuring only good dies are used in the final stack.
Implementation Method 1
a via array electrically connected to the contact pads; a semiconductor substrate configured to have vias of the via array electrically conductive with each other or insulated from each other
Implementation Method 2
a first type well formed at a first height from the bottom of a semiconductor substrate; second type doping regions formed within the first type well at the bottoms of regions where vias are expected to be formed
Data Source
AI summary
There are proposed a stack type semiconductor device and a method of fabricating and testing the same. A stack type semiconductor device according to an embodiment of the present invention includes a plurality of contact pads externally exposed, a via array electrically connected to the contact pads, a semiconductor substrate configured to have vias, forming the via array, electrically conductive with each other or insulated from each other, and a bias pad configured to supply a bias to the semiconductor substrate, wherein the semiconductor substrate may be subject to back-grinding.