Semiconductor Via Structure for Void-Free Contact Plug Connection

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Solution Overview

Problem

In semiconductor manufacturing, particularly for FinFETs, the formation of voids in vias can lead to increased resistance and reduced performance due to the limitations of conventional deposition processes.

Innovation Solution

A semiconductor structure and method involving a via landing on and extending over two contact plugs, with a bottom-up deposition process used to form a top via portion that grows from the metal surface of the bottom via portion, facilitating the creation of void-free vias and reducing contact resistance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional deposition processes are used to form vias, then the manufacturing process is simple, but voids form in the vias leading to increased resistance

Engineering Contradiction:
Improvevia qualityVSAvoidvia fill quality
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The via formation process is divided into two distinct stages: first forming a bottom via portion, then forming a top via portion that grows upward from the bottom portion. This segmentation allows each portion to be optimized independently, with the bottom portion providing a solid foundation and the top portion filling the upper via region, thereby eliminating voids that would occur in conventional single-stage deposition

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The bottom via portion is formed in advance as a preliminary structure before forming the top via portion. This preliminary action creates a solid metal foundation at the bottom of the via, which then serves as the base from which the top via portion grows upward, ensuring complete void-free fill without requiring complex subsequent processing

Inventive Principle:
Principle #10Preliminary action

2Manufacturing precision

If conventional deposition processes are used, then the process complexity is low, but contact resistance increases due to void formation

Engineering Contradiction:
Improvevia fill qualityVSAvoiddeposition process complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The deposition process is segmented into two sequential operations: forming a bottom via portion, then forming a top via portion that grows from the bottom portion. This segmentation achieves complete void-free via fill, eliminating contact resistance issues while keeping each individual deposition step relatively simple and compatible with existing manufacturing equipment

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The bottom via portion acts as an intermediary structure between the via opening and the underlying contact plug. By forming this intermediate metal structure first, it provides a solid foundation that enables subsequent complete filling of the top via portion, mediating the transition from partial to complete via fill without requiring fundamentally new deposition technology

Inventive Principle:
Principle #24Intermediary (Mediator)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enhances the performance of semiconductor devices by minimizing resistance through the formation of void-free vias, thereby improving the overall efficiency of the semiconductor structure.

Implementation Method 1

The top via portion is formed using a bottom-up deposition process, and may grow from the metal surface provided by the bottom via portion in the deposition process

Methodology Applied
Scientific EffectDeposition: Deposition (physical)

Data Source

PatentUS20240347594A1Semiconductor structure and method for forming the same
Publication Date: 2024.10.17 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US20240347594A1 patent drawing
  • US20240347594A1 patent drawing
  • US20240347594A1 patent drawing

AI summary

A method for forming a semiconductor structure is provided. The method for forming the semiconductor structure includes a first contact plug and a second contact plug through a first dielectric layer, forming a second dielectric layer over the first contact plug, the second contact plug and the first dielectric layer, etching the second dielectric layer to form a first opening exposing the first contact plug, the second contact plug and the first dielectric layer, forming a bottom via portion in the first opening, forming a third dielectric layer over the bottom via portion and the second dielectric layer, etching the third dielectric layer to form a second opening exposing the bottom via portion, and forming a top via portion in the second opening. The top via portion and the bottom via portion form a first via.