Semiconductor Via-Wiring Structure for Flat Bonding Surfaces

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Solution Overview

Problem

The connection reliability of the wiring layer in semiconductor devices is insufficient due to concave parts forming in the via holes during electroplating, leading to unstable bonding with external components and reduced fluidity of bonding materials.

Innovation Solution

The wiring layer is separately formed from the vias, with electrolytic copper plating, and semiconductor elements are bonded using sintered materials to vias with tapered shapes and flat edges, ensuring a stable bonding surface.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If the wiring layer and via are integrally formed by electroplating, then the manufacturing process is simplified, but concave parts form in the wiring layer reducing connection reliability

Engineering Contradiction:
Improvemanufacturing process simplicityVSAvoidconnection reliability
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

The patent divides the wiring layer and via into separate components. The via is formed first as a protrusion from the insulating layer, then the wiring layer is formed separately on the insulating layer surface. This segmentation prevents the wiring layer material from flowing into via holes during electroplating, eliminating concave parts while maintaining manufacturing feasibility through sequential formation steps.

Inventive Principle:
Principle #1Segmentation

2Quantity of substance

If metal deposits along the inner wall surface of via holes during electroplating, then the via is formed, but concave parts denting in the wiring layer are created

Engineering Contradiction:
Improvemetal depositionVSAvoidwiring layer surface flatness
Core Design Contradiction:
Quantity of substanceVSShape

Solution Approach 1:

The patent performs preliminary action by forming the via protrusion from the insulating layer before forming the wiring layer. This preliminary formation of the via structure prevents metal from flowing into via holes during subsequent electroplating of the wiring layer, thereby maintaining the flatness of the wiring layer surface without compromising via formation.

Inventive Principle:
Principle #10Preliminary action

3Manufacturing precision

If concave parts exist in the wiring layer, then via holes are formed, but fluidity of bonding material is reduced causing voids

Engineering Contradiction:
Improvevia hole formationVSAvoidbonding material voids
Core Design Contradiction:
Manufacturing precisionVSObject-generated harmful factors

Solution Approach 1:

By segmenting the via and wiring layer into separate components formed at different stages, the patent eliminates concave parts in the wiring layer. This ensures a flat bonding surface that maintains proper fluidity of bonding materials during external component bonding, preventing void formation while still achieving precise via hole formation through the separate via protrusion structure.

Inventive Principle:
Principle #1Segmentation

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enhances the bonding strength and reliability of the wiring layer by maintaining material fluidity and preventing voids, thus improving electrical and mechanical connections.

Implementation Method 1

A via hole is formed in an insulating layer and an adhesive agent layer, and further electroplating is performed on the other surface of the insulating layer and an inner wall surface of the via hole

Methodology Applied
Scientific EffectElectroplating: Electroplating

Data Source

PatentUS20250210534A1Semiconductor device and manufacturing method of semiconductor device
Publication Date: 2025.06.26 SHINKO ELECTRIC IND CO LTD
  • US20250210534A1 patent drawing
  • US20250210534A1 patent drawing
  • US20250210534A1 patent drawing

AI summary

A semiconductor device includes an insulation base material, a wiring layer, a via, and a semiconductor element. The insulation base material includes an insulating layer including an adhesive agent layer formed on one surface of the insulating layer. The wiring layer is formed on the one surface of the adhesive agent layer. The via is separately formed from the wiring layer and penetrates through the insulating layer and the adhesive agent layer, to be connected with the wiring layer. The semiconductor element is connected, via a sintered material, with another end of the via on an opposite side of one end of the via, the one end being connected with the wiring layer, on another surface of the insulating layer.