Semiconductor Device Vialess Pad Structure Alignment
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The existing semiconductor device manufacturing process is adversely affected by metal pads, leading to misalignment and increased contact resistance due to differences in occupying rates between regions, resulting in voids and joint failures during bonding.
Innovation Solution
The semiconductor device employs a vialess structure with pairs of large and small metal pads on both substrates, arranged in a specific lattice pattern to minimize occupying rate differences and prevent misalignment, thereby reducing contact resistance and preventing voids and joint failures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If metal pads are used for bonding, then electrical connection is achieved, but misalignment and contact resistance increase due to occupying rate differences
Solution Approach 1:
The bonding pad structure is segmented into two distinct layers: a first bonding pad on the first substrate and a second bonding pad on the second substrate. The second bonding pad has a smaller area than the first bonding pad, creating a stepped configuration. This segmentation allows each pad to be optimized independently for its function while maintaining overall alignment accuracy.
Solution Approach 2:
The patent applies different pad sizes at different locations in the bonding interface. The first bonding pad has a larger area to provide sufficient bonding surface and electrical contact area, while the second bonding pad has a smaller area to accommodate layout constraints on the second substrate. This local differentiation resolves the contradiction by allowing each region to have the quality it needs.
2Reliability
If metal pads are used for bonding, then electrical connection is achieved, but contact resistance increases due to occupying rate differences
Solution Approach 1:
The bonding interface is segmented into a first bonding pad with larger area and a second bonding pad with smaller area. This segmentation ensures that the first pad provides sufficient contact area to minimize resistance, while the second pad can be precisely positioned to avoid misalignment. The stepped configuration maintains good electrical contact while accommodating manufacturing tolerances.
Solution Approach 2:
The patent changes the geometric parameter (area) of the bonding pads to optimize electrical performance. By making the first bonding pad larger than the second, the design increases the effective contact area for current flow, thereby reducing contact resistance. This parameter change directly addresses the contradiction between connection reliability and resistance control.
3Ease of manufacture
If uniform pad size is used, then manufacturing is simplified, but occupying rate differences cause misalignment and voids
Solution Approach 1:
Rather than using uniform pads, the design segments the bonding interface into two pads of different sizes. This segmentation allows the larger first pad to compensate for any misalignment or void formation, ensuring reliable bonding even when manufacturing tolerances exist. The simpler fabrication process is maintained while bonding quality is improved through this asymmetric configuration.
Solution Approach 2:
The larger first bonding pad acts as a cushion or buffer zone that compensates for potential misalignment or void formation during bonding. By providing extra bonding area beyond what is strictly necessary, the design beforehand cushions against manufacturing variations, ensuring reliable bonding without requiring extremely tight tolerances.
Data Source
AI summary
In one embodiment, a semiconductor device includes a lower interconnect layer including a plurality of lower interconnects, and a plurality of lower pads provided on the lower interconnects. The device further includes a plurality of upper pads provided on the lower pads and being in contact with the lower pads, and an upper interconnect layer including a plurality of upper interconnects provided on the upper pads. The lower pads include a plurality of first pads and a plurality of second pads. The upper pads include a plurality of third pads provided on the second pads and a plurality of fourth pads provided on the first pads, a lower face of each third pad is larger in area than a upper face of each second pad, and a lower face of each fourth pad is smaller in area than a upper face of each first pad.