Semiconductor Void Cavities Reduce Gate-Drain Capacitance
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In semiconductor devices and integrated circuits, excess gate-drain capacitance (Cgd) limits device performance due to capacitive coupling, and existing methods to reduce it have been unsuccessful in achieving low enough dielectric constants using conventional materials.
Innovation Solution
The formation of void cavities within semiconductor devices with a dielectric constant similar to that of empty space, achieved through anisotropic and isotropic etching processes, which reduces the dielectric constant between the gate and drain regions, thereby minimizing Cgd.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional low dielectric constant materials are used in region 39 between bottom 31 of gate 30 and N DRIFT space 26, then some reduction in gate-drain capacitance Cgd is achieved, but the dielectric constant k is still significantly larger than vacuum or air, limiting further performance improvement
Solution Approach 1:
The patent changes the fundamental parameter of dielectric constant by replacing conventional solid dielectric materials (with k significantly larger than vacuum) with a void cavity filled with vacuum or air (k close to 1.0). This drastic parameter change enables maximum reduction of gate-drain capacitance Cgd, directly improving device performance by eliminating the limitation of conventional low-k materials.
2Object-generated harmful factors
If a void cavity is formed in the semiconductor substrate to reduce gate-drain capacitance, then capacitive coupling between gate and drain is minimized, but the fabrication process becomes more complex requiring multiple etching steps and precise control
Solution Approach 1:
The patent segments the cavity formation process into distinct anisotropic and isotropic etching steps. The anisotropic etching first creates a preliminary cavity with controlled depth and shape, then the isotropic etching removes additional material to achieve the final void cavity geometry. This segmentation allows precise control over cavity dimensions while maintaining fabrication feasibility.
Solution Approach 2:
The patent performs preliminary action by forming a preliminary cavity through anisotropic etching before completing the void cavity formation. This preliminary cavity serves as a template and protection structure during subsequent processing steps, enabling precise control over the final cavity geometry and preventing damage to surrounding structures.
3Object-generated harmful factors
If the void cavity is formed deeper in the substrate to maximize capacitance reduction, then gate-drain capacitance Cgd is further minimized, but manufacturing precision and control become more difficult to maintain
Solution Approach 1:
The patent performs preliminary action by forming a preliminary cavity through anisotropic etching with precise depth control before completing the void cavity formation. This preliminary cavity serves as a template and protection structure during subsequent processing steps, enabling precise control over the final cavity geometry and preventing damage to surrounding structures.
Solution Approach 2:
The patent segments the cavity formation process into distinct anisotropic and isotropic etching steps. The anisotropic etching first creates a preliminary cavity with controlled depth and shape, then the isotropic etching removes additional material to achieve the final void cavity geometry. This segmentation allows precise control over cavity dimensions while maintaining fabrication feasibility.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces gate-drain capacitance, improving device performance by reducing capacitive coupling and enhancing the figure of merit Ron*Qg, allowing for faster operation and better overall device performance compared to using low permittivity dielectric regions.
Implementation Method 1
achieved through anisotropic and isotropic etching processes
Implementation Method 2
achieved through anisotropic and isotropic etching processes
Data Source
AI summary
Field effect devices and ICs with very low gate-drain capacitance Cgd are provided by forming a substantially empty void between the gate and the drain regions. For vertical FETS a cavity is etched in the semiconductor (SC) and provided with a gate dielectric liner. A poly-SC gate deposited in the cavity has a central fissure (empty pipe) extending through to the underlying SC. This fissure is used to etch the void in the SC beneath the poly-gate. The fissure is then closed by a dielectric plug formed by deposition or oxidation without significantly filling the etched void. Conventional process steps are used to provide the source and body regions around the cavity containing the gate, and to provide a drift space and drain region below the body region. The etched void between the gate and drain provides lower Cgd and Ron*Qg than can be achieved using low k dielectrics.