Semiconductor Package Void Placement for Degassing and Signal Integrity
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Solution Overview
Problem
Current strategies for determining void placement in semiconductor packages do not simultaneously consider manufacturing design rules, electrical constraints, and degassing effects, leading to unoptimized designs with excessive voids that degrade electrical and thermal performance.
Innovation Solution
A three-phase void placement method that dynamically models design features, degassing rules, and copper balancing while adhering to manufacturing and electrical guidelines, optimizing void position, count, shape, and size to reduce void density and improve signal integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If excess voids are added to provide moisture escape paths and avoid blistering, then manufacturing performance is improved, but electrical performance degrades due to increased voltage drop and resistance
Solution Approach 1:
The patent changes the parameters of void placement by using dynamic modeling to determine optimal void positions, counts, shapes, and sizes based on manufacturing rules and electrical constraints. This resolves the contradiction by finding the precise parameter set that satisfies both manufacturing reliability (moisture escape) and electrical performance (minimal voltage drop) requirements, rather than using excess voids as a conservative approach.
Solution Approach 2:
The patent creates a virtual model (copy) of the semiconductor package design that includes all manufacturing rules, electrical constraints, and degassing requirements. This virtual model allows optimization of void placement without affecting the physical design, enabling identification of the optimal void configuration that balances manufacturing performance and electrical performance.
2Reliability
If excess voids are added to provide adequate degassing, then manufacturing performance is improved, but signal integrity deteriorates due to increased changes in transmission line impedances
Solution Approach 1:
The patent optimizes void placement parameters (position, count, shape, size) using dynamic modeling that incorporates transmission line impedance constraints. This resolves the contradiction by determining the minimum necessary voids with optimal parameters that provide adequate degassing while minimizing impact on signal integrity and transmission line impedance.
Solution Approach 2:
The patent performs preliminary void placement optimization during the design phase using virtual modeling, before final manufacturing. This allows identification and placement of voids in optimal positions that satisfy degassing requirements while minimizing impact on signal integrity, rather than adding excess voids as a precaution.
3Ease of manufacture
If current strategies are used for void placement, then manufacturing constraints are met, but the design becomes unoptimized with excessive numbers of voids
Solution Approach 1:
The patent uses a virtual model (copy) of the package design to simulate and optimize void placement. This virtual modeling approach allows comprehensive evaluation of manufacturing rules, electrical constraints, and degassing requirements simultaneously, identifying the minimum necessary voids with optimal placement, thereby reducing void quantity while maintaining ease of manufacture.
Solution Approach 2:
The patent dynamically optimizes void parameters (position, count, shape, size) based on manufacturing rules and design constraints. This resolves the contradiction by finding the optimal parameter set that satisfies manufacturing ease requirements while minimizing the number of voids needed, eliminating excessive voids from the design.
4Reliability
If more voids are placed in power metal planes, then moisture escape paths are improved, but thermal performance deteriorates due to concentrated high-density current regions
Solution Approach 1:
The patent optimizes void parameters (position, count, shape, size) using dynamic modeling that incorporates thermal performance considerations. This resolves the contradiction by determining the minimum necessary voids with optimal parameters that provide adequate moisture escape paths while minimizing disruption to current distribution and thermal performance in power metal planes.
Data Source
AI summary
A method of semiconductor modelling includes determining for a virtual model of a layer of a semiconductor package, wherein the layer includes a metal layer, one or more first regions of the layer that do not satisfy a first layer design rule; adding first voids to the one or more first regions to satisfy the first layer design rule; determining for the layer including the metal pattern and the first voids, one or more second regions of the layer that do not satisfy a second layer design rule, different from the first layer design rule; and adding second voids to the one or more second regions to satisfy the second layer design rule.