Semiconductor Device Integrating Volatile and Non-Volatile Memory
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Solution Overview
Problem
The integration of processors and non-volatile memory devices on separate chips leads to data integrity issues, security concerns, and slow data processing speeds due to wiring delays caused by parasitic resistance and capacitance in the bus line, especially during power interruptions.
Innovation Solution
A semiconductor device with a processor incorporating both volatile and non-volatile registers, an encryption circuit for compressing and encrypting data, and a non-volatile memory device, where data is verified upon power resumption to ensure integrity and security, allowing for integration on a single chip and reducing data transfer over the bus line.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If data is transferred between processor and non-volatile memory device via bus line, then data can be saved and restored, but wiring delay due to parasitic resistance and capacitance reduces data processing speed
Solution Approach 1:
The patent merges the processor and non-volatile memory device into a single integrated chip structure. The non-volatile memory device is directly coupled to the processor chip, eliminating the external bus line connection. This integration removes parasitic resistance and capacitance from the data transfer path, thereby eliminating wiring delays while maintaining data integrity between the processor and memory components.
2Reliability
If processor and non-volatile memory device are provided on separate chips, then data security can be maintained through encryption, but data transfer speed is reduced due to bus line wiring delay
Solution Approach 1:
The patent combines the processor and non-volatile memory device on a single chip while incorporating an encryption circuit within the integrated structure. This allows data to be encrypted during internal transfers without requiring external bus line communication, thus maintaining data security through encryption while eliminating the speed penalty associated with external bus line wiring delays and parasitic effects.
3Speed
If volatile register and non-volatile register are used in processor, then data can be saved and restored at high speed, but data integrity is degraded during power interruption
Solution Approach 1:
The patent implements a mechanism where data is preliminarily saved from the volatile register to the non-volatile memory device before power interruption occurs. The system detects power stop conditions and triggers a data transfer operation that moves critical data from the volatile register (which would lose data on power loss) to the non-volatile memory device (which retains data without power). This preliminary action ensures data integrity is maintained during power interruptions while minimizing the impact on processing speed through efficient integrated data paths.
Data Source
AI summary
An object is to solve all of the following problems caused when a volatile register and a non-volatile register are used as registers in a processor: degradation of the integrity of data stored in the non-volatile register; loss of data security due to the processor and a non-volatile memory device that are provided apart from each other; and slow data processing speed due to wiring delay or the like caused by these devices provided apart from each other. When data maintained in the volatile register is stored in the non-volatile register before supply of power supply voltage is stopped, the data is encrypted by an encryption circuit and stored in a non-volatile memory device that is provided separately from the processor. Then, the data stored in the non-volatile register is compared with the compressed and encrypted data stored in the non-volatile memory device.