Semiconductor Common Voltage Bus Stress Buffer Layer
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Solution Overview
Problem
Conventional semiconductor packages face reliability issues due to high residue stress from large area thick conductive materials, which can damage IC active circuitry and increase manufacturing costs through expensive processing steps like CMP, CVD, and RIE for forming peripheral input/output pads.
Innovation Solution
A semiconductor device with a stress buffer layer and a metal layer providing a common voltage bus, connected via wirebonds, is fabricated using a method that includes forming a passivation layer, a stress buffer layer, and a seed layer over the wafer, with the metal layer patterned to expose contact pads for electrical communication, reducing stress and eliminating the need for expensive peripheral pad formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If large area thick conductive materials are used for common voltage buses, then electrical conductivity is improved, but residue stress increases causing damage to IC active circuitry
Solution Approach 1:
The conductive material is segmented into multiple thinner layers (first conductive layer, second conductive layer, third conductive layer) instead of using a single thick layer. This segmentation maintains the overall conductivity while reducing the stress concentration that would occur in a monolithic thick structure, thereby preventing damage to the underlying IC active circuitry.
Solution Approach 2:
The patent employs a composite structure consisting of multiple conductive layers with different properties. Each layer serves a specific function: the first layer provides conductivity, the second layer acts as a stress barrier, and the third layer provides additional conductivity and structural support. This composite approach optimizes both electrical performance and stress management.
2Manufacturing precision
If expensive processing steps like CMP, CVD, and RIE are used for forming peripheral input/output pads, then manufacturing precision is improved, but manufacturing cost increases
Solution Approach 1:
The conductive layers formed during the bulk device fabrication process serve multiple functions: they provide electrical connectivity for the active devices, form the common voltage buses, and create the peripheral input/output pads. By making the conductive structure multi-functional, the patent eliminates the need for separate, expensive pad formation processing steps while maintaining high manufacturing precision through the existing fabrication processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The stress buffer layer minimizes stress-induced damage, improves package reliability, and reduces manufacturing costs by eliminating the need for costly processing steps, resulting in a more efficient and cost-effective semiconductor device production.
Implementation Method 1
forming a stress buffer layer over the passivation layer... The stress buffer layer minimizes stress-induced damage
Implementation Method 2
plating a metal layer over the semiconductor die. The metal layer provides a common voltage bus
Implementation Method 3
forming a seed layer over the wafer... The seed layer is in electrical communication with the contact pads
Data Source
AI summary
A semiconductor wafer contains a plurality of semiconductor die. The wafer has contact pads formed over its surface. A passivation layer is formed over the wafer. A stress buffer layer is formed over the passivation layer. The stress buffer layer is patterned to expose the contact pads. A metal layer is deposited over the stress buffer layer. The metal layer is a common voltage bus for the semiconductor device in electrical contact with the contact pads. An adhesion layer, barrier layer, and seed layer is formed over the wafer in electrical contact with the contact pads. The metal layer is mounted to the seed layer. Solder bumps or other interconnect structures are formed over the metal layer. A second passivation layer is formed over the metal layer. In an alternate embodiment, a wirebondable layer can be deposited over the metal layer and wirebonds connected to the metal layer.