Semiconductor IC Voltage Control Circuit for Ground Bounce Noise Reduction
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Solution Overview
Problem
Semiconductor ICs face increasing leakage currents and ground bounce noise due to abrupt current variations during power gating, which affects chip size and performance.
Innovation Solution
A semiconductor IC with a voltage control circuit that includes a power gating circuit with stepwise voltage increase, using transistors and a capacitor to manage power supply and reduce noise, and a control block to regulate the power gating circuit based on detected voltage and external commands.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If sleep transistors are turned on sequentially with time delays to reduce ground bounce noise, then ground bounce noise is reduced, but chip size becomes much larger due to many delay units required
Solution Approach 1:
The patent introduces a capacitor as an intermediary element connected between the sleep transistor and ground. This capacitor acts as a noise filter that suppresses ground bounce noise without requiring multiple delay units, thereby reducing chip size while still achieving noise reduction.
Solution Approach 2:
The patent changes the operational parameters of the sleep transistor by controlling its gate voltage through a specific voltage sequence. Instead of using multiple delay units, the gate voltage is adjusted in stages (from 0V to intermediate voltage to full voltage), achieving gradual power restoration and noise reduction with a single transistor structure.
2Object-affected harmful factors
If two sleep transistors are connected in series with a capacitor to block abrupt current variation, then ground bounce noise is reduced, but chip performance degrades due to voltage drop
Solution Approach 1:
The patent dynamically changes the gate voltage parameter of the sleep transistor during the power restoration process. The gate voltage transitions from 0V (off state) to an intermediate voltage (partial conduction) to full voltage (full conduction), allowing controlled current flow that reduces noise while maintaining sufficient voltage for chip performance.
Solution Approach 2:
The patent implements a periodic voltage application sequence to the sleep transistor gate, where voltage is applied in controlled stages rather than abruptly. This periodic control allows the capacitor to charge gradually, filtering noise while the transistor progressively opens to maintain performance.
3Speed
If power is supplied abruptly to activate a standby block, then activation speed is improved, but ground bounce noise increases causing malfunctions
Solution Approach 1:
The patent performs preliminary action by pre-charging the capacitor connected to the sleep transistor gate before fully activating the transistor. This preliminary charging of the capacitor prepares the circuit for gradual power restoration, enabling faster activation while preventing abrupt current surges that cause ground bounce noise.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Minimizes leakage currents and power consumption while reducing ground bounce noise, maintaining chip performance and size by gradually increasing voltage during power supply transitions.
Implementation Method 1
a capacitor having one electrode that is connected to the second and third transistors and the other electrode that is grounded
Data Source
AI summary
A semiconductor IC includes a logic block, and a voltage control circuit controlling an operating voltage supplied into the logic block. The voltage control circuit controls the operating voltage to be increased in a stepwise fashion during an initial operation of the logic block.