Semiconductor Storage Voltage Control for Current Peak Reduction
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Solution Overview
Problem
Semiconductor storage devices, such as NAND flash memory, face a high load on the controller due to repeated program and verify operations during data writing, which can lead to increased power consumption and potential damage from high current peaks during the verify operation.
Innovation Solution
The semiconductor storage device includes a control circuit that adjusts the rate of voltage increase on non-selected word lines during the verify operation, reducing the peak current by varying the slope of voltage change across multiple loops, thereby reducing the load on the memory controller.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the voltage applied to non-selected word lines is increased rapidly during verify operation, then the verify operation can be performed efficiently, but high current peaks occur causing damage and increased power consumption
Solution Approach 1:
The patent applies dynamics by making the voltage increase rate variable rather than fixed. The control circuit dynamically adjusts the voltage increase rate for non-selected word lines based on the loop number, transitioning from a constant rate to a variable rate that decreases as loops progress. This resolves the contradiction by enabling efficient verify operations initially while preventing damaging current peaks in later stages.
Solution Approach 2:
The patent changes the voltage parameter characteristics by modifying the voltage increase rate (slope) as a variable parameter. Instead of maintaining a constant voltage increase rate, the system changes this parameter based on the loop number, setting different rates for different loops. This allows the system to balance verify efficiency with current peak prevention by adapting the voltage application characteristics to the operational stage.
2Device complexity
If the voltage increase rate on non-selected word lines is kept constant across loops, then the control logic is simple, but high current peaks occur in later loops causing controller damage
Solution Approach 1:
The control circuit incorporates dynamic behavior by adjusting the voltage increase rate based on the loop number. This adds complexity to the control logic but is a manageable complexity that enables the system to prevent damaging current peaks. The dynamic adjustment is implemented through a control circuit that selects different voltage increase rates from a set of predetermined rates, balancing complexity with reliability.
Solution Approach 2:
The system uses feedback from the loop number (operation stage information) to determine the appropriate voltage increase rate. The control circuit receives information about which loop is currently executing and automatically selects the corresponding voltage increase rate. This feedback mechanism enables automatic adaptation without requiring complex external control, protecting the controller from damage while maintaining reasonable circuit complexity.
3Loss of time
If high voltage is applied to non-selected word lines during verify operation, then the verify operation completes faster, but power consumption increases and causes heat generation
Solution Approach 1:
The patent applies periodic action by varying the voltage increase rate in a periodic manner across different loops. Each loop uses a specific voltage increase rate appropriate to its stage, creating a periodic pattern of voltage application. This allows the system to maintain faster verify operations in early loops while reducing power consumption and heat generation in later loops through reduced voltage increase rates.
Data Source
AI summary
[Problem] To provide a semiconductor storage device capable of reducing the load on a controller.[Solution] According to one embodiment, a semiconductor storage device 2 includes a memory cell array 110 including a plurality of memory cell transistors MT, a plurality of word lines WL connected to gates of the respective memory cell arrays 110, a voltage generation circuit 43 generating a voltage applied to each of the word lines WL, and a sequencer 41 controlling an operation of the memory cell array 110. The sequencer 41 repeats a loop including a program operation and a verify operation multiple times in a write operation. The sequencer 41 controls an operation of the voltage generation circuit 43 so that a rate increase in a voltage applied to a non-selected word line in the verify operation of a last loop is smaller than the rate increase in the voltage applied to the non-selected word line in the verify operation of a first loop.