Semiconductor Voltage Generation Using Register Bits
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Solution Overview
Problem
As the number of program states in NAND memory cells increases, existing semiconductor devices struggle to generate the necessary voltage levels with sufficient accuracy and variety for efficient operations like programming, reading, and erasing, particularly requiring more verification and read voltages.
Innovation Solution
The introduction of additional bits stored in a register unit and combined with control bits using a combination circuit to generate enable signals, which are then used by a voltage generation circuit to produce a wider range of voltage levels, allowing for more precise and varied voltage outputs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of program states is increased to enhance memory capacity, then the memory capacity increases, but the number of voltage levels that must be generated increases proportionally, making voltage generation more complex
Solution Approach 1:
The voltage generation control is segmented into two independent parts: control bits (generated in response to command signals) and additional bits (stored in register units). This segmentation allows the voltage generation circuit to handle multi-level voltage requirements without increasing overall system complexity, as each segment can be managed separately through dedicated circuits.
Solution Approach 2:
The patent introduces an additional dimension to the control signal structure by adding additional bits to the traditional control bits. This dimensional expansion allows the system to generate a larger number of voltage levels (e.g., 256+ levels) without increasing the complexity of the base control circuit, effectively solving the contradiction between memory capacity and voltage generation complexity.
2Measurement precision
If more voltage levels are generated to support more program states, then more accurate voltage differentiation is required, but existing control circuits cannot generate sufficient voltage levels with adequate precision
Solution Approach 1:
The patent merges control bits and additional bits through a combination circuit to form combined control signals. This merging allows the voltage generation circuit to receive comprehensive control information that encompasses both the command-based control bits and the register-stored additional bits, enabling precise generation of a large number of differentiated voltage levels required for multi-state memory operations.
Solution Approach 2:
The combination circuit serves as an intermediary between the control bits and additional bits, and the voltage generation circuit. It combines these two separate control elements into unified enable signals that precisely control the voltage generation circuit to produce the required variety of voltage levels with accurate differentiation.
3Adaptability or versatility
If additional control bits are used to generate more voltage levels, then the number of controllable voltage levels increases, but the device size increases proportionally
Solution Approach 1:
The additional bits are stored in advance in register units during a preliminary action phase. This allows the voltage generation circuit to access pre-stored control information when needed, eliminating the need for real-time generation of additional control bits and reducing the overall device area by using compact register storage instead of larger control logic circuits.
Solution Approach 2:
The patent uses register units to store copies of additional bits that are associated with command signals. These stored copies can be selectively read and combined with control bits without requiring the physical presence of the original signal sources, thereby reducing device area while maintaining full voltage level control capability.
Data Source
AI summary
A semiconductor device includes a register unit for storing additional bits associated with a command signal and outputting a selected additional bit corresponding to a received address; a combination circuit for combining received control bits and the selected additional bit, and outputting enable signals based on the combined bits, where the received control bits are generated in response to the command signal and a control signal; and a voltage generation circuit for outputting voltages distributed in response to the enable signals.