Semiconductor Internal Voltage Measurement Circuit

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Solution Overview

Problem

Conventional methods for measuring the developing time of a reference voltage in semiconductor memory devices are prone to precision issues due to loading caused by probe tips and parasitic loads, making it difficult to accurately determine this critical parameter for system design.

Innovation Solution

A semiconductor device with an internal voltage generation unit, enable setting logic, monitoring unit, and measurement result signal generation unit that allows for precise measurement of the developing time of an internally-generated reference voltage without distortion, using a DC-level signal output to define the starting and ending points of voltage generation and measurement.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If a test device or oscilloscope with probe tip is used to measure the developing time of reference voltage, then measurement can be performed externally, but measurement precision deteriorates due to loading caused by probe tip and parasitic loadings

Engineering Contradiction:
Improvedeveloping time measurement precisionVSAvoidloading effect from probe tip
Core Design Contradiction:
Measurement precisionVSObject-affected harmful factors

Solution Approach 1:

The patent introduces an intermediary measurement circuit consisting of a capacitor and comparator that acts as a buffer between the reference voltage generation circuit and the external measurement device. This intermediary circuit captures the voltage development process internally without requiring direct connection via probe tip, thereby eliminating the harmful loading effect while maintaining measurement capability

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent creates a copy of the reference voltage development process by using a capacitor to store and replicate the voltage transition. The comparator then monitors this copied voltage signal, allowing external measurement of the developing time without the probe tip directly loading the original reference voltage circuit

Inventive Principle:
Principle #26Copying

2Measurement precision

If conventional external measurement methods are used, then measurement capability is provided, but measurement precision is compromised due to parasitic loadings

Engineering Contradiction:
Improvedeveloping time measurement precisionVSAvoidmeasurement system complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The measurement system performs self-service by incorporating the measurement functionality directly into the semiconductor device. The internal capacitor and comparator circuit automatically capture and monitor the reference voltage development, generating measurement signals without requiring complex external test equipment or multiple measurement probes

Inventive Principle:
Principle #25Self-service

3Measurement precision

If probe tip connection is made to measure reference voltage developing time, then external measurement is enabled, but measurement accuracy is reduced due to loading effects

Engineering Contradiction:
Improvedeveloping time measurement accuracyVSAvoidmeasurement reliability
Core Design Contradiction:
Measurement precisionVSReliability

Solution Approach 1:

The capacitor-comparator measurement circuit serves as a reliable intermediary that accurately captures the voltage development timeline without the reliability issues associated with external probe connections. This intermediary structure ensures consistent and reliable measurements by eliminating variable contact resistance and loading effects

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS8674752B2Semiconductor device and method for driving the same
Publication Date: 2014.03.18 MIMIRIP LLC
  • US8674752B2 patent drawing
  • US8674752B2 patent drawing
  • US8674752B2 patent drawing

AI summary

A semiconductor device includes an internal voltage generation unit configured to generate an internal voltage in response to an enable signal, an enable setting logic unit configured to define a starting time point for generating the internal voltage in response to the enable signal, a monitoring unit configured to monitor whether or not the internal voltage reaches a target level, and define an ending time point for generating the internal voltage in response to the monitoring result, and a measurement result signal generation unit configured to generate a measurement result signal corresponding to a developing time of the internal voltage in response to an output signal of the enable setting logic unit and an output signal of the monitoring unit.